JPS6342097A - Multi-level logic storage circuit - Google Patents

Abstract

PURPOSE:To allow a simple circuit constitution to attain a great noise margin by storing voltages corresponding to n-kind of currents on the side of a driving circuit in a 1st current mirror circuit and generating logic signals on the side of a load circuit in a 2nd current mirror circuit according to the stored voltages. CONSTITUTION:In writing data, n-kind of currents Iw are allowed to flow to the side of the driving circuit 12 in the 1st current mirror circuit 11 according to write data, and the voltages of values corresponding to the currents conducted to the side of the load circuit 13 are stored in a memory cell 16. In reading data, currents corresponding to the voltages stored in the memory cell 16 are allowed to flow to the side of the driving circuit 13 in the 2nd current mirror circuit 17, and a logic signal generator circuit 19 connected to the side of the load circuit 8 in the 2nd current mirror circuit 17 generates the logic signals 20 corresponding to the current values at that time. Thus data can be written and read at high speed with a great noise margin.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an n-value logic storage circuit, and particularly to a multi-value logic storage circuit that writes and reads data in current mode. Regarding.

(Prior Art) Semiconductor memories, especially dynamic random access memory circuits that store data in the form of charges, so-called DRA
M's memory capacity continues to increase rapidly as circuit technology and semiconductor manufacturing technology improve. However, the increase in storage capacity due to miniaturization of elements leads to a decrease in the capacity of charge storage capacitors, making it difficult to determine the storage state of data in memory cells.

In response to this, multivalued logic memory circuits are being researched as a means of increasing the number of memory users. This multivalued logic storage circuit can increase the amount of information per cell compared to a binary logic storage circuit, so it can be highly integrated. Furthermore, multilevel circuits are expected to be applied to functional devices that use multilevel functions.

However, most of the multi-valued logic memory circuits announced so far have been written and read in voltage mode, and have noise margins of 21! ! It has various disadvantages compared to logic. For example, a conventional multivalued logic memory circuit is
There are two types of memory cells: one that uses a CCD (charge-coupled device) and one that uses a one-transistor type similar to binary logic.In the former case, it is difficult to reduce the voltage because the charge transfer loss is large. There are problems such as high power consumption because it is necessary to drive an 8-way load.

Further, in the latter case, there is a problem that the operating speed is slow.

(Problems to be Solved by the Invention) As described above, the conventional multivalued logic memory circuit has drawbacks such as difficulty in reducing the voltage, high power consumption, and slow operation speed.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to be able to obtain a large noise margin with a simple circuit configuration, and also to be able to perform data 3-input and readout at high speed. An object of the present invention is to provide a multivalued logic storage circuit.

[Structure of the invention] (Means for solving the problems) Many features of this invention! [The logic memory circuit includes a first current mirror circuit having a drive circuit and a load circuit, current input means for flowing current of n different values to the drive circuit side of the first current mirror circuit, and the first current mirror circuit. It is connected to the load circuit side of the current mirror circuit, and includes a memory cell that stores a voltage of a value corresponding to the current flowing to the load circuit side, a drive circuit, and a load circuit. a second current mirror circuit through which current flows to the drive circuit side; and a logic signal generator that is connected to the load circuit side of the second current mirror circuit and generates a logic signal according to the value of the current that flows to the load circuit side. It consists of means.

(Function) In the multivalued logic storage circuit of the present invention, when writing data, currents of n different values are caused to flow to the drive circuit side of the first current mirror circuit according to the written data, and currents of n different values are caused to flow to the drive circuit side of the first current mirror circuit depending on the current flowing to the load circuit side. The value of the voltage is stored in the memory cell. Further, when reading data, a current corresponding to the voltage stored in the memory cell is passed through the drive circuit side of the second current mirror circuit, and a logic signal is generated that is connected to the load circuit side of the second current mirror circuit. The electricity i at this time is
Generates a logic signal according to *.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a multivalued logic storage circuit according to the present invention. In the figure, 11 is a first current mirror circuit. This first current mirror circuit 11
is composed of a drive circuit 12 and a load circuit 13,
A current input circuit 14 is connected to the drive circuit 12 side. This t-flow input circuit 14 has ng! expressed by a multi-bit binary logic signal supplied to an input terminal 15. A current Iv corresponding to a certain value of i logic is generated, and this current Iw is supplied to the drive circuit 12.

A memory cell 16 is connected to the load circuit 13 side of the first current mirror circuit 11. This memory cell 1
61.1 It is arranged at the intersection of the unillustrated dot lines and column lines that are selectively driven by an unillustrated X decoder (row decoder) and Y decoder (column decoder), and the row lines and column lines are selectively driven by an unillustrated address signal. A voltage having a value corresponding to the current flowing to the load circuit 13 side when selectively driven is stored as data. The voltage storage method in this memory cell 14 is based on a dynamic type in which charge is temporarily stored.

Further, 17 is a second current mirror circuit.

This second current mirror circuit 17 is a drive circuit 1 which is also used as a load circuit of the first current mirror circuit 11.
3 and a load circuit 18, the drive circuit 13
The memory cell 16 is connected to the side. and,
When reading data, the memory cell 16 generates a current IR corresponding to a voltage value stored in advance, and supplies this current to the drive circuit 13 of the second current mirror circuit 17.

A logic signal generation circuit 19 is connected to the load circuit 18 side of the second current mirror circuit 11. This logic signal generation circuit 19 detects the current IR' flowing to the load circuit 18 side of the current mirror circuit 17 when the readout control signal RO is supplied, and generates a binary logic signal according to the current value. . The binary logic signal generated by the logic signal generation circuit 19 is output from the output terminal 20.

As described above, since the above embodiment circuit performs data loading and reading in the current mode, it has various advantages such as high-speed loading and reading, large noise margin, and high reliability. It has the following advantages.

FIG. 2 is a circuit diagram specifically showing the circuit of the above embodiment, and parts corresponding to those in FIG. 1 are given the same reference numerals for explanation. The drive circuit 12 of the first current mirror circuit 11 has a source connected to a positive power supply voltage VDD.
Consisting of a channel MO8 transistor 21 and a P-channel MO3 transistor 22 whose source and drain are connected between the gate and drain of this transistor 21 and whose conduction is controlled when data is loaded into the memory cell 76. has been done. In addition, the load circuit of the first current mirror circuit 11 or the drive circuit 13 of the second current mirror circuit 17 has a source that has a positive polarity power supply voltage V
a P-channel MoS transistor 2 connected to DO and whose gate is connected to the gate of the transistor 21;
3, the source and drain are connected between the gate and drain of this transistor 23, and are made non-conductive when writing data to the memory cell 16, and when reading data from the memory cell 16. and a P-channel MOS transistor 24 whose conduction is controlled.

The load circuit 18 of the second current mirror circuit 17 is composed of a plurality of P-channel MO8 transistors 25 whose sources are connected to the positive power supply voltage DD and whose gates are connected in parallel to the gate of the transistor 23. ing. The output terminal 20 is connected to each transistor 2.
Connected to the drain of 5.

In the current input circuit 14, each drain is connected to a transistor 2 in the drive circuit 12 of the first current mirror circuit 11.
1, each source is commonly connected to the ground voltage Vas, and the gate is connected to each input terminal 15.
A plurality of N-channel MOS transistors 26 connected to
It consists of That is, in this embodiment, the current input circuit 14 has 21! This is for converting a logical signal of i into a current of n value.

The memory cell 16 is an N-channel MOS transistor 2 whose drain is connected to the drain of a transistor 23 in the load circuit 13 of the first current mirror circuit 11.
7, and an N-channel MOS transistor 28 whose drain is connected to the drain of the transistor 27 and whose source is connected to the gate of the transistor 27. The source of the transistor 27 is connected to one row I! 29, the gate of the transistor 28 is connected to one column line 30. Note that a P-channel transistor can also be used as the transistor 28.

The logic signal generation circuit 19 has a drain connected to the drain of each transistor 25 in the load circuit 18 of the second current mirror circuit 17, and a source connected to the earth voltage Vs.
s and whose gates are supplied with the readout control signal RO, and whose drains are the drains of the transistors 25 in the load circuit 18 of the second current mirror circuit 17. N-channel MOS transistors 32 whose sources are commonly connected to the ground voltage Vss and whose gates are respectively connected to all the output terminals 20 of the upper bits, whose sources are commonly connected to VDD and whose drains are connected to the above-mentioned The memory cell 1 is connected to the drain of each transistor 25 in the load circuit 18 of the second current mirror circuit 17.
N-channel MOS transistors 33 whose conduction is controlled when reading data from 6 and whose number is the same as that of transistors 25
It is made up of. Then, when the transistor 33 is turned on, each transistor 33 has the transistor 2
If the current flowing through the transistor 5 is logic 1, the element dimensions are set so that a current corresponding to logic "0.5" flows. Further, in this embodiment, the logic signal generating circuit 19 is used to convert an n-value current into a binary logic signal.

In such a configuration, when writing data, the transistor 22 in the drive circuit 12 of the first current mirror circuit 11 is made conductive, and the transistor 24 in the load circuit 13 is made non-conductive. As a result, input terminal 1
2 fed into 5! Current input circuit 1 according to I logic signal
A current In of one of the n values flowing through the transistor 21 flows through the transistor 21 .

For example, if the channel dimensions of transistors 21 and 23 are set equal, the current I of the same value is
rL flows through transistor 23 and is supplied to memory cell 16. In this memory cell 16, the row line 29 is set to the ground voltage in response to the address signal when data is enriched, and the column line 3 is set to the ground voltage.
0 is selectively set to the VDO voltage. That is, the gate of the transistor 28 is brought to a high potential and becomes conductive. However, in this case, an N-channel transistor is used as the transistor 28. Then, the current IrL flows between the source and drain of the transistor 27, and the gate voltage of the transistor 27 is maintained at a voltage corresponding to the connection state between the drain and the gate. In other words, transistor 2 at this time
■The gate voltage of 7. , the threshold W1 voltage is VT, the following equation holds between these.

1rL-β(VG-VT)2- Also, β is a proportionality constant. In other words, when writing data,
The voltage V given to the memory cell 16 by the relationship in equation 1 above is applied to the memory cell 16.
o is stored at the gate of transistor 27. After this,
When transistor 28 is rendered non-conductive, the gate voltage of transistor 21 is dynamically maintained.

On the other hand, when reading data, the transistor 22 in the drive circuit 12 of the first current mirror circuit 11
is made non-conductive, and transistor 24 in load circuit 13 is made conductive. In the memory cell 16, the row line 29 is set to the ground voltage. Then, due to the voltage accumulated at the gate of the transistor 27, a voltage 2R1n equal to the above corresponding to one value of nll is applied to the transistor 28.
and flows to transistor 23. At this time, in the logic signal generation circuit 19, the transistor 31 is rendered conductive by the read control signal RO, thereby generating a binary logic signal corresponding to the current IrL.

The detailed operation at the time of reading the data will be explained by taking as an example the case where the value of n is 4 as shown in FIG.

In addition, Fig. 4 shows the output terminal 200°20 of this Fig. 3 circuit.
1 is a characteristic diagram showing the relationship between the voltages of the binary logic signals Do and Dt obtained in Example 1 and the current I. FIG. In FIG. 4, broken line curves 41 to 43 indicate currents corresponding to logic values "1P,""2", and "3" of the memory cell 16, and solid line curves 44 to 47 indicate these curves. 41 to 43 and the logic value "0", the logic values "0" + "0.5", '1" + "°0. 5゛、
It shows the current corresponding to “2” + “0.5” and “3P +”0.5”, and the solid line curves 48 to 50
is the transistor 3 of the transistor 310°311 alone.
The static characteristics when No. 10 and No. 32 are connected in parallel are shown respectively.

The voltage at the intersection of these characteristics is the signal Do.

Terminal 20 as Dl. ．． 20. is output from.

First, when stored data with a logic value of "0" is read out, both signals Do become binary logic "yes".

When the stored data of logic field “1” is read out, the signal Do
is the voltage at the intersection of the curve 45 and the curve 1148, ie, the binary logic °H゛°, and Dl is the voltage at the intersection of the curve 45 and the curve 49, ie, the binary logic "L".

When the stored data with the logical value "2" is read out, the signal D1
becomes the voltage at the intersection of the curve 46 and the curve 49, that is, H" of binary logic. At this time, the transistor 32 becomes conductive due to this signal redirection, so the other signal Do becomes the voltage at the intersection of the curve 46 and the curve 49.
and transistor 31. and 32 are connected in parallel, the voltage at the intersection with the characteristic curve 50, that is, the binary logic L''.

When the stored data with logical value "3" is read out, the signal D1
is the voltage at the intersection of curve @47 and curve 49, i.e. 2fI
At this time, the transistor 32 becomes conductive due to this signal @Dt, so the other signal Do becomes the voltage at the intersection of the curve 48 and the characteristic curve 50, that is, the binary logic "H". Become.

In this way, the output terminal 20. ．． 20. The signals Do and Dl obtained from ′ is closer to Voo, ° “L” is closer to O■
, and data can be reliably output with a larger noise margin.

FIG. 6 shows the stored data in the circuit shown in FIG. 3 and the corresponding binary logic signal Do.

It is a figure which shows the truth value of Dl collectively.

The method using the four-value logic explained above can be extended to the n-value logic in the embodiment circuit of FIG.

In this way, according to the above embodiment, a memory circuit of any n-value logic can be configured. Moreover, there is an advantage that the design and manufacturing process are simple for any nil transistor, since only the shape of the transistor needs to be considered.

The above embodiment circuit has a large noise margin, high reliability, a simple memory cell configuration, and a small occupied area.
It has advantages such as short access time. These advantages will become clear in the description below.

When manufacturing the specific circuit shown in FIG. 2 above using CMOS process technology, the transistor 2 in the memory cell 16
The difference in characteristics between when an N-channel type was used and when a P-channel type was used was investigated. When the transistor 28 is an N-channel transistor, a well region is not required when configuring the memory cell 16, and the area occupied by the cell can be reduced, but the noise margin is reduced.

FIG. 7 summarizes the relationship between the write current 1 w s read current IR and the gate voltage Vo of the transistor 27 for each logic value when the transistor 28 is configured with an N-channel or P-channel MOS transistor with a power supply voltage Voo of 5V. It is a diagram.

As shown in the figure, when the transistor 28 is configured with a P-channel MO3) transistor, the write current is 1 w.
s read current IR and gate voltage Vo can be increased. Further, the transistor 28 is P channel, N channel
No matter which channel is configured, the values of write current 1w and read current IR are equal, and this is one of the factors that can improve reliability.

FIG. 8 shows each of the cases shown in FIG. 7 above, that is, when a H-channel MOS transistor is used as the transistor 28, and when a P-channel MoS transistor is used, and when the gate voltage Va is divided into three equal parts. It is a characteristic diagram when the write and read current I is divided into three equal parts. That is, FIG. 8(a) shows the gate voltage Vo when an N-channel MOS transistor is used as the transistor 28.
FIG. 8(b) is a characteristic diagram when the write and read current I is divided into three equal parts when an N-channel MOS transistor is used as the transistor 28, and FIG. FIG. 8(C) is a characteristic diagram when the gate voltage VG is divided into three equal parts when a P-channel MOS transistor is used as the transistor 28.
d) is a characteristic diagram when a P-channel MoS transistor is used as the transistor 28 and the read current I is divided into three equal parts. The reason why the noise margin is small when an N-channel MoS transistor is used is that the transistor 28 has a substantial Ia due to the back gate bias effect.
This is because the l value voltage increases and becomes non-conductive at a certain source voltage (gate voltage of transistor 27) that is smaller than Voo.

On the other hand, the P-channel MoS transistor is
8, it is possible to use Va up to VDD without the above-mentioned back gate bias effect, so a large noise margin can be secured. That is, when the write and read current I is divided into three equal parts, the noise margin can be as large as 36°5 μA.

Furthermore, in the above embodiment circuit, the logical values "O", "1",
The access time for “2” and “3” is the minimum line width of 5
When expressed in μm, 0 nanoseconds, 50 nanoseconds, and 68 nanoseconds, respectively.
It was a nanosecond, 28 nanoseconds.

In addition, the power consumption has logical values “0”, “1°′,” “2”
, 170μm#, 465μW for “3”, respectively.
They were 750 μW and 900 μW. Also, set the minimum line width to 1
/k, the access time will be approximately 1/2.
Furthermore, if we take into consideration the fact that it is possible to pursue optimal conditions, it is possible to construct a memory circuit that is extremely fast, consumes little power, and has excellent performance.

In addition, the above embodiment circuit is a normal binary 0MO8-LSI.
It can be manufactured using exactly the same process technology.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, although the circuit of the above embodiment has been described as being composed of MOS transistors, it is needless to say that the circuit is not limited to MOS transistors, but can also be composed of bipolar transistors.

In addition, in the above embodiment circuit, the input signal and the output signal are 2
Although the case where the value logic signal is used has been described, it goes without saying that this may be any multi-value signal, and the configuration of the current input circuit 14 and the logic signal generation circuit 19 can be changed depending on the multi-value signal used. Just change it.

[Effects of the Invention] As explained above, according to the present invention, a multi-level logic memory circuit is provided which can obtain a large noise margin with a simple circuit configuration and can also write and read data at high speed. can be provided.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram specifically showing the above embodiment circuit, and Fig. 3 is a block diagram showing the value of n in the circuit shown in Fig. 2 above. , a partially extracted circuit diagram; FIG. 4 is a characteristic diagram of the circuit shown in FIG. 3; FIG. The figure shows the truth value of the output signal of the circuit shown in Fig. 3 above, Fig. 7 shows the 1-inclusive, read current, and gate voltage of the circuit shown in Fig. 3 above, and Fig. 8 shows the circuit shown in Fig. 3 above. It is a characteristic diagram for explaining. DESCRIPTION OF SYMBOLS 11... First current mirror circuit, 14... Current input circuit, 16... Memory cell, 17... Second current mirror circuit, 19... Logic signal generation circuit, 21
．． 22.23.24°25,33...P channel MO
3 transistors, 26.27°28, 31.32...
N-channel MOS transistor, 29009 row line, 30
...row line. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Decoy Figure 3 Do, Dl Figure 4 Single power vo. Figure 5 Figure 6 Figure 7 (a) Figure 8 (b) (d)

Claims (1)

[Scope of Claims] 1. A first current mirror circuit having a drive circuit and a load circuit; current input means for flowing current of n different values to the drive circuit side of the first current mirror circuit; A memory cell that is connected to the load circuit side of the current mirror circuit No. 1 and stores a voltage having a value corresponding to the current flowing through the load circuit side, a drive circuit, and a load circuit, and stores the voltage stored in the memory cell. The second current flows to the drive circuit side.
and a logic signal generating means connected to the load circuit side of the second current mirror circuit and generating a logic signal according to the value of the current flowing to the load circuit side. Multivalued logic memory circuit. 2. The multivalued logic storage circuit according to claim 1, wherein the load circuit of the first current mirror circuit also serves as a drive circuit of the second current mirror circuit. 3. The memory cell includes a first MOS transistor whose source and drain are inserted on the load circuit side of the first current mirror circuit, and a source and drain which is inserted between the gate and drain of the first MOS transistor. a second MOS transistor which is inserted and whose conduction is controlled only when writing data, and a voltage having a value corresponding to the current flowing to the load circuit side of the first current mirror circuit at the gate of the first MOS transistor. 2. The multivalued logic storage circuit according to claim 1, which is configured to store . 4. On the load circuit side of the second current mirror circuit, N circuits each having one end connected to the power supply (N=l_0g_2
n) load elements are provided in parallel, the other ends of each of these N load elements are connected to the output terminal of each bit signal, and the logic signal generating means is connected to the output terminal of the second current mirror circuit. One MOS transistor each having one end between the source and drain connected to the other end of each of the N load elements and whose conduction is controlled during logic signal conversion, and the other end of the corresponding one of the N load elements. A multi-level MOS transistor according to claim 1, comprising a MOS transistor in which one end between a source and a drain is connected in common, and a gate is respectively connected to the output terminals of all bits higher than that bit. Logic memory circuit. 5. The logic signal generating means includes means for adding to each load element a current corresponding to 0.5 in terms of a logical value of the current flowing through each of the N load elements of the second current mirror circuit. A multivalued logic storage circuit according to claim 4 provided.