JPS6356553B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a display device that performs display using a display device such as a liquid crystal display. When connecting a display device and an integrated circuit element including a random access memory etc. that derives the signal to be displayed on the display device using a signal line, make sure that the signal lines do not intersect as much as possible. It is desirable to reduce or eliminate through holes in the substrate. A typical prior art is shown in Japanese Patent Application Laid-Open No. 52-134330. In this prior art, the display panel is composed of two small panels, one of which has a row electrode group in which every other row electrode is extracted, and a column electrode group in which every other column electrode is similarly extracted. Consisting of
The other small panel is composed of a row electrode group made up of the remaining row electrodes and a column electrode group made up of the remaining column electrodes, and these two small panels are arranged so that they are slightly shifted and overlapped. This makes it possible to connect the row and column electrodes relatively easily. In this prior art, no effort has been made to simplify the connection between each row and column electrode and a drive circuit element such as a memory that stores display information. An object of the present invention is to provide a display device in which a display device and a drive circuit element that provides signals to the display device can be easily connected to each other without crossing the signal lines connecting the two. That's true. The present invention has a plurality of segments, selects every other sequential segment electrode and divides them into two groups, and collects input terminals individually connected to the segment electrodes of each group into each group. and output terminals S individually corresponding to the segment electrodes.
0 to S63, select every other output terminal corresponding to the sequential segment electrodes and divide them into two groups, and output terminals S0, S2, S4, corresponding to the segment electrodes of each group individually. ...,S
62; includes a drive circuit element chip1 in which S1, S3,..., S63 are arranged together in each group, and this drive circuit element chip1 further includes sequential (for example, column A random access memory 4 stores display data (sequential); and a random access memory 4 stores display data stored in the random access memory 4, selecting every other column (for example, of a column) and dividing the display data into two (for example, even and odd columns).
The display data belonging to one group of display data and the other group of display data (for example, in the embodiment described later, 32 pieces of display data for each back plate HO) are simultaneously displayed. And the shift registers 5A, 5B form a pair that are stored individually, and the outputs of each shift register 5A, 5B are sent to output terminals S0, S2, ..., S62 for each two groups;
Circuits 19A, 19B for driving the segment electrodes by leading to S1, S3, S5, ..., S63;
9A and 9B. FIG. 1 is a perspective view of one embodiment of the present invention.
The large-scale integrated circuit chip 1 includes a circuit for driving a display device 2 using liquid crystal, and these circuits are attached to a wiring board (not shown). Input terminals S1a and S of one group G1a of the two groups are provided on both sides of the terminal board 3 of the display 2.
3a, S5a, ..., S63a and input terminals S0a, S2a, S4 of another group G0a
a,..., S62a are arranged. This display 2
has the segment electrodes described below, and every other segment electrode to be driven sequentially is selected sequentially and divided into two G1a and G0a, which are individually connected to the segment electrodes of each group. Input terminals S0a to S63a are arranged on both sides of the terminal board 3 as shown in the figure. The circuit configuration within the large-scale integrated circuit chip 1 is shown in FIG. This large-scale integrated circuit basically includes a random access memory 4 for storing display signals, shift registers 5A and 5B for extracting the stored contents of the random access memory 4 as display signals, and a register for forming display signals. A serial/parallel conversion circuit 6 that transfers data between the counters c and h and a circuit provided outside the large-scale integrated circuit chip 1, a chip select control circuit 7, and an auto clear that controls the display state immediately after power is turned on. It includes a circuit 8, drivers 9A and 9B for driving the display 2, and a clock generation circuit 10.
There are 16 large-scale integrated circuit chips 1, as described in connection with FIG. 39 below, and the 39th
In the figure, those integrated circuits are referenced chip1 to chip1.
6. Chip select control circuit 7
are large-scale integrated circuits chip1 to chip16 that should operate in response to signals input from terminals CS0 to CS3.
Activate. (1) Random access memory 4 In this embodiment, the random access memory 4 has a storage area of 64 bits horizontally by 20 bits vertically, as shown in FIG.
is shown. The display 2 has as many display bits as the storage area for each bit, as shown in FIG. 3. Each bit of the random access memory 4 and each dot of the display 2 correspond individually. In the following description, components and signals provided to the components may be designated by the same reference numerals. In Figure 2, l3, l4, l5, l20
indicates the number of bits of the signal line. In FIG. 3, reference signs AD0 to AD7 are signals for representing addresses of random access memory, among which signals AD0 to AD5 are used for row selection, and signals AD6 and AD7 are used for column selection. used. Among the timing signals H0 to H19 of the back plate of display unit 2, (a)
Timing signals H0 to H7 correspond to AD6=0 and AD7=0 when selecting columns, (b)
Timing signals H8 to H15 correspond to address signals AD6=1, AD7=0 for column selection, and (c) timing signals H16 to H19 correspond to address signals AD6=0, AD for column selection.
It corresponds to 7=1. Segment electrodes S0 to S63 of the display device 2 correspond to address signals AD0 to AD5 for row selection. 4 to 8 show random access memory 4
and its associated circuit configuration. Each cell of the random access memory 4 is divided into an even number group 4a and an odd number group 4b by selecting and grouping every other address sequentially derived in timing order. Address signal A0 is used for column selection. The signals from the cells of the even group 4a are sent to the aforementioned output terminals S0, S2,
It is derived from S4,...,S62. The signals from each cell of the odd group 4b are sent to the aforementioned output terminal S.
1, S3, S5, ..., S63. Signals from the cells in the even group 4a are led out to the shift register 5A, signals from the cells in the odd group 4b are led out to the shift register 5B,
Data transfer takes place. The address signal given to the random access memory 4 is obtained as follows. The address controller 11 is supplied with signals from each cell A1-A5 of an 8-bit register A having cells A0-A7, and also receives signals from each cell C0-C4 from a 5-bit counter c having cells C0-C4. A signal is given. The data selector 12 includes cells A0, A6, A7 of register A and cells h0 to h.
A signal from a 5-bit counter h consisting of 4 is given. Cells C0 to C4 and cells h0 to h4 are
It is used to sequentially take out the contents of the random access memory 4 and form serial signals SR0 and SR1 for display. Cells A0 to A7 are provided to random access memory 4 only when data is transferred to and from the outside, and are constituted by flip-flops. Therefore, normally, cells C0-C4 and cells h0-h4 are used for address and data selection of random access memory 4 for display purposes, and data transfer from the outside is performed in the form of an interrupt. At the time of this interruption, an address signal that is completely different from the address signal from which the display signal should be derived is given, so during that time the display signal may be disturbed and the display 2 may not be able to display normally. In order to solve this problem, the present invention provides latch-type flip-flops 13 and 14 (see FIGS. 5 and 6) that function as an output buffer for the random access memory 4 in the data selector 12. Correct display is always provided on the display 2 even if data transfer is interrupted from the outside. The signal CS in FIG. 7 is the output signal obtained from the flip-flop CS shown in FIG.
When CS = 1, the large-scale integrated circuit chip 1 is selected, and when CS = 0, the large-scale integrated circuit chip 1 is selected.
1 is not selected. Signals RAS and RAF are signals that are generated only when transferring data from the outside. When signal RAS is generated when CS = 1, address signals A1 to A7 are used to select the address and data of random access memory 4. Switched to operation. When CS=0 or signal RAS is not generated, signals from cells C0 to C4 of counter c are applied to address decoder 15, which derives a signal for row selection of random access memory 4, and column selector 16 are given signals from cells h3 and h4 of counter h. Counters c and h are counters used to generate display signals as described later. A group selector 17 and a read/write controller 18 are connected to the column selector 16 for selecting the even group 4a and the odd group 4b. A write clock WR is input to the read/write controller 18. Signals Ni, Mi (i=0 to 7) from the group selector 17 are applied to the flip-flop 1 shown in FIGS.
3 and 14, and the outputs ni and mi are used in the circuit of FIG. In this way, the signal SR0 is obtained by the circuit shown in FIG. Another signal SR1 is obtained in exactly the same way. Referring to FIG. 9, the signal RAS is shown in FIG. 91, the signal RAF is shown in FIG. 92, and the signal used for the address of the random access memory 4 obtained thereby. is determined as shown in FIG. 9. The configuration of the electrodes in the display 2 is as shown in FIG. 10, where the segment electrodes are designated with the same reference numbers S0 to S63 as the signals, and the back plate is designated with the same reference numbers H0 to H19 as the signals. has been done. FIG. 11 is a waveform diagram showing the output state of counter c, and FIG. 12 is a waveform diagram showing the output state of counter h. Referring to these drawings, for example, while a signal for driving back plate H19 is being generated, cells h0 to h4 are "0", and for column selection of random access memory 4, AD6=0, AD7=0. h0=h
Since 1=h2=0, signal SR0 has m0, that is, even group 4 of random access memory.
The 0th bit line of a is cell C0 of counter c
The output from C4 is scanned to obtain serial data. The same applies to signal SR1.
While the back plate H19 is being generated in this way, the display data to be derived during the generation period of the signal for the next back plate H0 is shifted into the shift registers 5A and 5B, and from the signal H19 to the H
It is latched and derived when switching to 0. Thereafter, by sequentially incrementing the counter h, the contents of the random access memory can be taken out as a display signal. When displaying data in the random access memory 4, random access is performed according to the count values of a counter c counted by the reference clock φ1 and a counter h clocked by the clock φS, which is the carrier signal of the counter c. Addressing memory 4 (Figures 3, 4, 11 and 12)
(see figure). The output from this random access memory 4 is outputted via a group of flip-flops 13 and 14 whose set condition is the signal φN, and further supplied to shift registers 5A and 5B via the gates shown in FIG. Display driver 9
A, 9B are supplied. Referring again to FIG. 9, when data is transferred from the outside to random access memory 4, signals RAS and RAF are generated. flipflop 1
3 and 14 (see Figures 5 and 6) are flip-flops whose clock operates as φN=・, and CS=
0 or when the signal RAF is not generated, that is, when φN = HIGH, the contents of the input signals Mi and Ni are output as they are, and when CS = 1 and the signal RAF is generated, that is, when φN = LOW, the data is held. do. Therefore, even if the signals RAS and RAF are generated during data transfer with the outside and the output from the random access memory 4 changes to a different content, the previous correct display data is transferred to the flip-flop 13,
14 can be stored. This prevents the display signal from being disturbed during interrupts. signal
The reason why RAF is configured to temporally include the signal RAS is that the address switching of the random access memory 4 is performed by the signal RAS, and the change in the output signal of the random access memory at the time of this switching is detected by the flip-flop 13. , 14. The signals RAS and RAF will be explained in detail later. (2) Shift registers 5A, 5B As a means of extracting the stored contents of the random access memory 4 as a display signal, the output from the random access memory 4, which is normally output in bytes, is converted into a serial signal, and this is sent to the shift register 5A. , 5B, and is latched in latch circuits 19A and 19B using a clock φS synchronized with the display signal to obtain a segment signal. As shown in FIG. 2, the shift register is divided into two blocks 5A and 5B, one shift register 5A has an odd numbered segment, and the other shift register 5B
are constructed corresponding to even numbered segments. The reason why the shift registers 5A and 5B were divided into even and odd numbers was because of the large-scale integrated circuit.
This is to similarly divide the output terminal of chip 1 into two, an even number and an odd number, for output. As mentioned above, FIG. 10 is a diagram showing the pattern of the electrodes in the display device 2 according to the present invention. According to the idea of the present invention, it is possible to display kanji characters and graphics. In this case, if the number of segments is large and you try to give signals to the segment electrodes from the input terminals S0a to S63a, the first
As shown in the figure, it is necessary to take out every other item in upper and lower parts. Therefore, input terminals S0a to S6
3a and the output terminals S0 to S63 without crossing each other.
The numbers are also divided into even and odd numbers. Furthermore, another reason for dividing into two groups is to reduce the power consumption of the large-scale integrated circuits chips 1 to 16. By dividing into two groups, only 32 clocks are required to transfer data from random access memory 4 to shift registers 5A and 5B. If it is not divided, 64 transfer clocks will be required, and in order to create 64 transfer clocks within a certain period of time, the basic oscillation frequency must be doubled. (complementary metal oxide film semiconductor), the amount of power is doubled. (3) Counters c, h FIGS. 11 and 12 show time charts of the counters h, c, and FIGS. 13 to 17 show details of the configurations of the counters h, c and their surroundings. The counter c shown in FIG. 13 performs a counting operation by the basic clock φ1 shown in FIG.
2, C1, C0 = 1, clock φS is 11th
This occurs as shown in FIG. A signal H is input to the reset terminal of the counter c, and synchronization is achieved by this signal H. Counter c is a 32-decimal counter. 11 2 to 11 6 show the signal C
The waveforms of 0 to C4 are shown respectively. The clock φS is obtained by the AND gate shown in FIG. The counter h shown in FIG. 14 is φS in FIG. 12
It is a counter whose clock is , but it can be reset by
It is given by HR=H+HOR. H is a signal for synchronization, and the signal HOR in FIG. 12 is determined by the output from register N having cells N0 to N3. 12 2 to 12 6 show the waveforms of signals from cells h0 to h4, respectively,
FIG. 12 shows the waveform of the signal HS. The value of register N can be set externally, and the read-only memory consisting of a matrix shown in FIG. 16 is a circuit that generates a reset signal HOR for counter h based on the value of register N. In the waveform diagram of FIG. 12, the signal HOR is h4,
Occurs at the timing of h3, 2, h1, h0,
The counter h is in 20 decimal. The flip-flop 21 shown in FIG. 17 for deriving the signal HS
is synchronized with the clock φS, and the input is H・(HS
HOR), it is synchronized by signal H and is inverted for each signal HOR. As is clear from the above, the count number of the counter h determines the duty of the back plates H0 to H19. Therefore, register N is
This is a register for duty setting. Further, the signal HS is a signal for configuring an alternating voltage. (4) Serial/parallel conversion circuit 6 All internal data processing is performed in parallel, and data is transferred serially to the outside, so serial/parallel conversion is required. Register L
is a shift register with serial/parallel out, parallel in, and serial out functions. FIG. 38 1 shows the signal CL0, FIG. 38 2 shows the waveform of the signal LC, and FIG. 38 shows the waveform of the signal RAS.
Reference code SD0 is a serial data bus, CL0 is a serial transfer clock, and LC is a synchronization signal. The 8-bit data serially transferred from the outside via terminal SD0 is temporarily stored in register L shown in Figure 18, and then stored in internal random access memory 4.
address, chip select and duty data, and data written to the random access memory 4. When taking out the contents of the random access memory 4, the data in the random access memory 4 is first input in parallel to the register L, and then taken out as serial data to the outside by a shift function. In order to distinguish between the above types of data transfer, 2 bits are added before the 8-bit serial data, and 4 types of ``00'', ``01'', ``10'', and ``11'' are detected and each data Allow the transfer to occur. Here, "00" is writing duty and chip select data, "01" is writing address data of random access memory 4, "10" is writing data of random access memory 4, "11" is random Read data from access memory 4. After writing or reading data in the random access memory 4,
Register A for the address of random access memory 4 is automatically incremented by +1. This is to prevent the complexity of addressing each time in continuous data transfer with the random access memory 4. 19 to 36 show details of the serial/parallel conversion circuit 6. Further, FIGS. 37 and 38 show time charts of serial data transfer. The serial data transfer operation is as shown in FIG. 37 1 and FIG. 38 1.
Using CL0 as the basic clock, the process starts from the rising edge of the signal LC shown in FIG. 37 and FIG. 38.
37.1 shows the waveform of signal CL0, FIG. 37.2 shows the waveform of signal LC, and FIG. 37.3 shows the waveform of signal SD.
37.4 to 37.7 show the output waveforms from cells K0 to K3. FIG. 37.8 and 37.9 show the waveforms of signals φLS0 and φLS1, respectively. 10 and Figure 37 1
1 shows the waveforms of the signals LS0 and LS1, respectively, FIG. 37 shows the waveforms of the signals K3 and K2, FIG. 37 shows the waveform of the signal RAS, FIG. 37 shows the waveform of the signal RAF, FIG. 37 15 shows the waveform of the signal FL, and FIG. 37 16 shows the waveform of the signal SDD. The counter K shown in FIG. 19 is a 4-bit binary counter, performs a counting operation while the signal LC is "1", and is reset when the signal LC becomes "0". Counter K counts from 0 to 14, completing a series of serial data transfers. The data is 8 bits, but 2 bits are added in front,
Distinguish between types of data. Signal φLS0 in Figure 20
And φLS1 shown in FIG. 21 is a clock that receives the contents of this control 2 bits.
Flip-flops 22, 2 in FIGS. 2 and 23
3 statically stores two control bits (contents of bits PA and PB in FIG. 37) in the serial data transfer section. φL obtained by the configuration of FIG. 31 is the clock of register L, and the count K is 2, 3, 4, 5, 6, 7, 8,
This is the clock that appears at 9 and 12, and the previous 8
The register L performs a shift operation, and the last clock is a clock that takes in the contents of the built-in random access memory 4. This distinction is made by the K3-K2 signals that control the input gates of register L. The signal RAS shown in FIG. 24 has a counter K of 10,
Between 11 and 12, the RAF shown in Figure 25 is 9, 10, 11,
12 and 13, and the signal RAS is used as a clock for chip selection, duty writing, and address writing, and is also used as an address switch when writing and reading data to the random access memory 4. used. Signal RAF is as described in paragraph (1). The signal SD0 in FIG. 29 is a bidirectional data line and is normally an input, but becomes an output when the flip-flop 27 in FIG. 30 is at "1". As shown in the time chart of FIG. 38, the signal SDD is the output from the flip-flop 27 that is set only when reading out the data in the random access memory 4, and the control 2
This is a signal that is set after a bit is applied until the end of transfer in order to transmit the serial signal of data in the random access memory 4 to the outside. Chip select and duty writing Referring to the time chart in Fig. 38, Fig. 38 4 shows the waveform of the signal SD0, and Fig. 38 5 shows the signal SD0 waveform.
38 shows the waveform of LS0, FIG. 38 shows the waveform of 7SDD, and FIG. 38 shows the waveform of signal φCS. When sending control 2 bits “00”, LS0=0, LS1
= 0, and the clock φCS is generated by the configuration shown in FIG. At the rising edge of clock φCS,
Register L has completed shifting of 8 bits of serial data following the control bits, and 8 bits of serial data following the control bits have been shifted.
The contents of the top 4 bits L4 to L7 are as follows:
A specific configuration is shown in FIG. 32. Written to register N. Furthermore, as shown in the input conditions of the flip-flop 28 from which the signal CS is derived in FIG. If you have,
Flip-flop 28 is set and reset if there is a mismatch. In other words, when chip select data is transferred to large-scale integrated circuit chip 1, which has many connected chips, the flip-flop CS of chip 1 selected is set to match this code,
All other flip-flops 28 of chips 2-16 that do not match this code are reset. Here, if L4=L5=L6=L7=1, the 27th
As shown, signal φCS is inhibited. This is because only when this code is used, setting of chip select and duty is prohibited and auto clear is canceled. Address writing and data transfer to the random access memory 4 shown below are valid only when the flip-flop 28 is set. Writing Address Data Figure 9 shows the waveform of the signal LD0.
FIG. 10 shows the waveform of signal LS0, FIG. 38 shows the waveform of signal LS1, and FIG. 38 shows the waveform of signal LS1.
The waveform of SDD is shown, and FIG. 38 shows the waveform of signal φA. When the control 2 bit "01" is applied, LS0=0 and LS1=1, and the clock φA is generated by the configuration shown in FIG. Signal φA
At the rising edge of , the 8 bits of serial data following the control bit have been shifted to register L, and as shown in FIG. 38, LS0=
0, the inputs of address flip-flops A0 to A7 shown in FIG. 35 become cells L0 to L7, and address data is written therein. Writing data to random access memory 4 Figure 38 shows the waveform of signal SD0, and
8 Figure 15 shows the waveform of signal LS0, Figure 38 16
shows the waveform of signal LS1, and Fig. 38 shows the waveform of signal LS1.
38 shows the waveform of SDD, FIG. 38 shows the waveform of signal WR, and FIG. 38 shows the waveform of signal φA.
When control 2 bits “10” are given,
LS0=1, LS1=1, and the write clock WR for random access memory 4 becomes the 34th clock.
This occurs as shown in the figure. The signal WR is a clock generated during the signal RAS, and while the signal RAS is output, the 8 bits of serial data following the control bit have been shifted to the register L, as shown in Figure 2. Signals L0 to L7 are applied as inputs to random access memory 4 and written into random access memory 4 by clock WR. At this time, the address is the signal RAS
According to the configuration shown in FIGS. 35 and 36, signals A0 to A7 are given to the address decoder 15 and column selector 16, and data is written to the addresses shown by the signals A0 to A7. . Here, the clock φA is generated when the counter K is at a position of 13. Since LS0=1, register A is incremented by +1 by this signal φA. This is internal random access memory 4
When writing data continuously, the address is incremented by +1 just by writing the data without having to specify the address each time, and data can be transferred quickly without having to specify the address each time. Reading data from random access memory 4 FIG. 38 shows the waveform of signal SD0, and the third
8. Figure 21 shows the waveform of signal LS0, and Figure 38.2
2 shows the waveform of the signal LS1, FIG. 38, 23 shows the waveform of the signal SDD, and FIG. 38, 24 shows the waveform of the signal φA. When the control 2 bit "11" is sent, LS0 = 1, LS1 = 0, and the flip-flop 27 that derives the signal SDD from the next bit of the serial data is set, and as shown in FIG. The least significant bit L0 of L is given, and the contents of register L are shifted by clock φL and sent to the terminal as serial data.
Given externally from SD0. Here register L
The data of the random access memory 4 shown in register A is stored in . This is due to the following reason. Before data is read from the random access memory 4, the four operations shown in FIG. 38 are always performed. What these four operations have in common is that the clock φL and signal RAS in FIG. 38 are always applied. At the rising edge of the last clock φL, the signal RAS is output to the random access memory 4, so the address signals A0~
A7 is given, and the contents of the random access memory 4 indicated by A0 to A7 are output as outputs O0 to O7 of the random access memory 4. On the other hand, as shown in FIG. 18, signals O0 to O7 are applied to the inputs of register L, and when the last clock of signal φL rises, register L receives signals A0 to A7. The contents of random access memory 4 are read. Therefore, when reading data from the random access memory 4 is started, register L has the following information:
The contents of the random access memory 4 are always stored, and the data contents of the random access memory 4 can be read by shifting and taking out the data. In this way, the data contents can be read from the random access memory 4. The reason why the clock φA is generated at the end of reading data from the random access memory 4 is exactly the same as when writing data to the random access memory 4. (5) Chip select control circuit 7 The segment signal of large-scale integrated circuit chip1 is S
There are 64 large-scale integrated circuits chips 0 to S63, and normally a plurality of these large-scale integrated circuit chips 1 to 16 are used. In this case, in order to select one large-scale integrated circuit from among multiple chip select terminals CS0 to
CS3 is provided. 4 chip select terminals
Up to 16 large-scale integrated circuits by CS0 to CS3
Chip1 to chip16 can be connected. Here, a feature of the present invention is that there is no need to connect a signal line from the outside as a chip select signal, and
All you need to do is connect it to the power supply level. Figure 39 shows 16 large-scale integrated circuits chip1~
The case where chip16 is connected is shown, but even in this case, the signal lines are SD0, CL0, φ,
Only H is enough. VA, VB, as power line
Vcc, GND, and VDISP are required. Maximum large-scale integrated circuit chips 1 to 16 with a total of 10 lines
Up to 16 devices can be connected, which is very useful in terms of packaging density. As shown in Figure 28, the flip-flop CS
When flip-flop CS is set, this large-scale integrated circuit chip 1 is in a selected state, and when flip-flop CS is reset, it is in a non-selected state. Chip select data is externally applied as a serial signal to cells L0 to L3 of register L, and the contents of cells L0 to L3 at this time and chip select terminals CS0 to
If the contents of CS3 match, flip-flop
CS is set; if there is a mismatch, flip-flop CS is reset. When the address data of the random access memory 4 and data write and read signals to the random access memory 4 are sent, the large-scale integrated circuit chip 1 set in the flip-flop CS receives them.
The large-scale integrated circuit chips 2 to 16 whose flip-flop CS has been reset are not accepted. The flip-flop CS has a clock φCS obtained by the configuration shown in FIG. 6 and FIG. 27.
is given. The details of the conditions for setting and resetting the flip-flop CS are as described above. In the foregoing and subsequent descriptions, for convenience, flip-flops and signals derived from the flip-flops are sometimes referred to by the same reference numerals. (6) Auto Clear One feature of the present invention is that the back plate, segment signals, and duty are controlled externally by software. It takes time for this to occur, and during that time, the display 2 will not be able to display normally, which may seriously damage the image of the product.
Therefore, in the present invention, after the power is turned on, the internal flip-flop ALC shown in FIG. However, it is maintained in a dormant state. In FIG. 40, reference symbols P and N indicate P channel and N channel, respectively. To reset the flip-flop ALC,
This is done using an external signal, and in this embodiment, when a code for "1111" is sent with the duty setting, the flip-flop ACL is reset without setting the duty. Therefore, after turning on the power, use the software to set the back plate and segments to their initial values, set the duty, and then reset the above-mentioned flip-flop ACL to return the display 2 from the idle state to normal display operation. You can move to In flip-flop ACL, Vcc is the 41st
When given as shown in FIG. 1, the AA point becomes the waveform shown in FIG.
It is set to "1" as shown in FIG. This state is maintained until a reset input is received. As mentioned in connection with FIG.
ACL is input to shift registers 5A and 5B
This is a signal that cuts off SRφ and SR1, and while the flip-flop ACL is maintained at "1", data "0" is given to shift registers 5A and 5B, so the display remains in a dormant state. flip flop
To release the ACL, when the code corresponding to the duty is selected as "1111" in the chip select and duty writing in FIG. 38, the reset signal Reset shown in FIG. 40 is generated and the flip-flop ACL is released. (7) Drivers 9A, 9B Drivers 9A, 9B are shown in Figures 42 and 43.
Show details. The inputs of the shift registers 5A and 5B are a signal HS, a signal SR0, and a signal HS.
and EXCLUSIVE OR of signal SR1 are given. This is to create an inverted signal in accordance with the period of the signal HS. The clocks φ1 and φS are the first
This is the same as the clocks φ1 and φS shown in the time charts of FIGS. 1 and 12. Signals SR0 and SR1 converted into serial data are shifted to shift registers 5A and 5B by clock φ1, and latched to the next stage flip-flop by clock φS. Signals SG0~ in Figures 42 and 43
SG63 is a segment signal latched in synchronization with clock φS. #1 and #2 are liquid crystal driver cells, the structures of which are shown in FIGS. 45 and 46, respectively. Here, Fig. 46 shows a segment driver for display 2, while Fig. 45 shows a driver that can be used for both segment and backplate purposes, and can be used as either a segment or a backplate by simply changing the mask of large-scale integrated circuit chip 1. It is a driver cell. The cell designated by reference numeral 32 and cells like it serve as transfer switches. In this embodiment, driver cell #1 is connected to output terminals S0 to S19, and output terminals S0 to S1
9 can be output as a back plate or as a segment. Figure 47 shows the power supply for the reference number #3 driver shown in Figure 44, and Figure 50 shows the connections of VA, VB, and VM.
Figure 1 shows the display time chart. Also the 48th
The diagram and FIG. 49 show connections when the #1 type driver cell is selected for the segment or back plate. In these drawings, (SGi),
() and () indicate signals obtained by level-converting the signal SGi, . In FIG. 51, the back plate signal is shown in FIG. 51, and the segment signal is shown in FIG.
1 is shown in FIG. 2, and FIG. 51 shows the levels VA, VB,
VM, signal HS is shown in FIG. 51, signal SG0
are shown in FIG. 51, respectively. Here, the feature of the present invention is that the backplate signal and the segment signal are distinguished only by selecting the output as either the backplate type or the segment type in the final driver section, and the data in the random access memory 4 The advantage is that backplates and segments can be treated in the same way. FIG. 52 shows the data arrangement of the random access memory 4 when signals S0 to S19 are applied to the back plate. In this case, register N
Data is set so that the duty is 1/20, and the counter h counts as shown in FIGS. 11 and 12. Back plate H19
At the timing of A7A6=00, the 0th bit line of the random access memory 4 is transferred to the shift registers 5A and 5B, and the latch clock φS outputs signals SG0 to SG63 from the flip-flop at the timing of the next back plate H0. . The driver corresponding to signal SG0 is now the fourth driver.
The configuration is shown in Figure 9. Inputs to shift registers 5A and 5B are SR0HS and SR1.
Since it is composed of HS, the output waveform of the signal SG0 becomes the waveform shown in FIG. 51, and becomes the backplate waveform shown in FIG. 51. Since the signals SG20 to SG63 are drivers shown as segments in FIG. 46, they have waveforms as shown in FIG. 51, for example, depending on their contents. By changing the setting of register N, the duty corresponding to display 2 can be changed arbitrarily. Also, the order in which signals are output to the back plate is
By changing the random access memory data 4, it can be changed arbitrarily. (8) Clock generation circuit 10 Each of the large-scale integrated circuits chips 1 to 16 has a built-in clock generation circuit 10 so that each of them can have a display function even when it is independent. Multiple large-scale integrated circuits
When connecting chips 1 to 16, one of them oscillates a clock using the clock generation circuit 10, and the remaining large-scale integrated circuits chips 2 to 16 oscillate a clock.
6 performs overall synchronization by receiving the basic clock and synchronization signals. φ shown in FIG. 2 is a basic clock, and H is a synchronization signal. Whether the basic clock φ and the synchronization signal H are generated or received can be changed by masking the large-scale integrated circuits chips 1 to 16. Counters h, c, and HS are asynchronous after power-on, but are synchronized by the first synchronization signal H. The synchronization signal H is a signal generated for each frame of the display 2, and synchronization is established for each frame. Counters h, c and
The first step is for the HS to be reset and synchronized.
As explained in connection with FIGS. 3 to 17, signal H is a signal generated by the circuit shown in FIG. 53, has the longest period among the repetitive signals, and has a pulse width equal to This is the same as one cycle of φ1. As shown in FIG. 53, there are two types of synchronizing signal H: one is supplied to the outside, and the other is supplied from the outside, and this can be switched by a mask. On the other hand, the first clock is used internally.
Although not shown in FIG. 53, in this embodiment, two-phase clocks φ1,
The internal circuit is configured by generating φ2. Second
φ shown in the figure is a basic clock that constitutes two-phase clocks φ1 and φ2, and these clocks φ1 and φ2
are asynchronous between each large-scale integrated circuit chip1 to chip16, but the two-phase clocks φ1 and φ2 are also synchronized by the above-mentioned synchronization signal H. FIG. 54 shows a two-phase clock generation circuit according to this embodiment. The signal HT is a signal generated by the signal H as shown in FIG.
This is to synchronize clocks φ1 and φ2. A time chart is shown in FIG. 56, showing that the phases of the clocks φ1 and φ2 relative to the signal H can be changed by the signal H. FIG. 56 1 shows the waveform of the clock φ, and FIGS. 56 2 to 4 show the waveform of the clock φ.
4 Signals a, b, c used in Figures 1 to 54 and 3
FIG. 56 shows the waveforms of the clock φ
1, FIG. 56 shows the clock φ2, FIG. 56 shows the synchronizing signal H, and FIG. 56 shows the signal H.
Indicates HT. A specific configuration of the circuit shown in FIG. 551 is shown in FIG. 552. As described above, according to the present invention, the input terminals corresponding to the sequential segment electrodes of the display are grouped into two groups, and the output terminals of the drive circuit elements are also grouped into two groups. By arranging the signal lines, there is no need to intersect the signal lines that are wired with each other, thereby eliminating the need for through holes in the wiring board, etc., and simplifying the wiring. Furthermore, according to the present invention, every other display data is selected sequentially from the random access memory 4 for storing display data and divided into two groups, and each display data belonging to each of the two groups of display data is divided into two groups. are stored simultaneously in the two shift registers 5A, 5B forming a pair, and individually in the shift registers 5A, 5B for each group, so there are, for example, a total of 64 pieces of data from the random access memory 4. If so, only 32 clocks are required to transfer them to the shift registers 5A and 5B. Therefore, if you want to create 64 transfer clocks within a certain period of time without dividing them into two groups, you would have to double the basic oscillation frequency, but according to the present invention, the frequency of the transfer clocks can be lowered. You will be able to do this. Therefore, the unique effect of being able to reduce the power consumption of the drive circuit elements is achieved.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a display device 2 and a large-scale integrated circuit chip 1 according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the large-scale integrated circuit chip 1 according to the present invention, and FIG. 3 is a random A diagram showing the storage area of the access memory 4, FIGS. 4 to 8 are block diagrams of the random access memory 4 and its related components, and FIG.
The figure is a waveform diagram for explaining the display operation by the display 2, FIG. 10 is a diagram showing the pattern of the display 2,
11 and 12 are waveform diagrams for explaining the operations of counters c and h, respectively. FIGS. 13 to 17 are block diagrams showing counters c and h and their related configurations. Figure 36 shows the series
37 and 38 are waveform diagrams for explaining the operation of serial/parallel data transfer.
The figure is a block diagram showing the connection state of large-scale integrated circuit chips 1 to 16, and Figure 40 is a flip-flop.
A block diagram showing the configuration of ACL, Figure 41 is
FIGS. 42 to 49 are block diagrams showing the configuration of drivers 9A and 9B, and FIG.
Figure 0 is a block diagram showing the connection state between the large-scale integrated circuit chip 1 and the power supply, Figure 51 is a waveform diagram of the signal used for display on the display 2, and Figure 52 is a diagram showing the connection state between the large-scale integrated circuit chip 1 and the power supply. A diagram showing the storage area of the random access memory 4 in the case of
FIG. 53 is a block diagram showing the configuration for generating the synchronizing signal H, FIGS. 54 and 55 are block diagrams showing the configuration for generating blocks φ1 and φ2, and FIG. 56 is the large-scale integrated circuit chip 1. FIG. 3 is a waveform diagram for explaining the synchronous operation of FIG. 2...Display unit, 4...Random access memory, 5A, 5B...Shift register, 6...Serial/parallel conversion circuit, 7...Chip select control circuit, 8...Auto clear circuit, 10...Clock generation Circuit, 11...Address controller, 12
...Data selector, 19A, 19B...Latch circuit, chip1 to chip16...Large-scale integrated circuit, A
...Register, c, h...Counter, CS...Flip-flop, S0 to S63...Output terminal, S
0a to S63a...input terminals.

Claims (1)

[Claims] 1. A device having a plurality of segments, in which every other segment electrode is selected sequentially and divided into two groups, and input terminals individually connected to the segment electrodes of each group are connected to each group. It has a display device that is arranged collectively for each segment electrode, and output terminals that individually correspond to the segment electrodes, and the output terminals that correspond to the sequential segment electrodes are selected every other and divided into two groups. a drive circuit element in which output terminals individually corresponding to segment electrodes of each group are arranged together for each group, and the drive circuit element further includes sequential display data corresponding to each segment electrode. The display data stored in the random access memory is selected every other and divided into two groups, and one group of display data and the other group of display data are divided into two groups. It is characterized by including a pair of shift registers that simultaneously and individually store the respective display data belonging to each other, and a circuit that derives the output of each shift register to the output terminals of each of the two groups and drives the segment electrodes. display device.