JPS6354769A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6354769A JPS6354769A JP9324886A JP9324886A JPS6354769A JP S6354769 A JPS6354769 A JP S6354769A JP 9324886 A JP9324886 A JP 9324886A JP 9324886 A JP9324886 A JP 9324886A JP S6354769 A JPS6354769 A JP S6354769A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- single crystal
- forming
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000013078 crystal Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 30
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 83
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000010894 electron beam technology Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- IWZSHWBGHQBIML-ZGGLMWTQSA-N (3S,8S,10R,13S,14S,17S)-17-isoquinolin-7-yl-N,N,10,13-tetramethyl-2,3,4,7,8,9,11,12,14,15,16,17-dodecahydro-1H-cyclopenta[a]phenanthren-3-amine Chemical compound CN(C)[C@H]1CC[C@]2(C)C3CC[C@@]4(C)[C@@H](CC[C@@H]4c4ccc5ccncc5c4)[C@@H]3CC=C2C1 IWZSHWBGHQBIML-ZGGLMWTQSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
〔発明の技！ｌｉ分野〕
本発明は、半導体膜置の製造方法に係わり、特に絶縁膜
上に形成した単結晶半導体膜にＭ ＯＳトランジスタを
形成するための半導体膜置の製造方法に関する。[Detailed description of the invention] [Technique of invention! FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor film device, and more particularly to a method for manufacturing a semiconductor film device for forming a MOS transistor in a single crystal semiconductor film formed on an insulating film.
〔発明の技ｔｊｉ的背貝とその問題点〕近年、半導体基
板上に堆積しｔ；絶縁膜上に単結晶半導体膜を形成する
技術が開発されている。この単結晶半導体膜は、絶縁膜
上に非晶質若しくは多結晶の半導体薄膜を１「積し、レ
ーザビームや電子ビーム等を用いて該半導体３膜をビー
ムアニールすることにより得られる。そして、絶縁膜上
に形成された単結晶半導体膜に″ｖ１０Ｓトランジスタ
等の半導体素子を形成し、素子を３次元的に形成する、
所謂３次元ＩＣの実現も可能となっている。[Background of Invention Techniques and Their Problems] In recent years, a technique has been developed for forming a single crystal semiconductor film on an insulating film deposited on a semiconductor substrate. This single crystal semiconductor film is obtained by stacking one amorphous or polycrystalline semiconductor thin film on an insulating film and beam annealing the three semiconductor films using a laser beam, an electron beam, etc. A semiconductor element such as a "v10S transistor is formed on a single crystal semiconductor film formed on an insulating film, and the element is formed three-dimensionally,"
It has also become possible to realize a so-called three-dimensional IC.
しかしながら、この種の方法にあっては次のような問題
があった。即ら、絶縁膜上にＭＯＳトランジスタ等の半
導体素子を形成する際、半導体素子の素子分離は一般に
素子形成領域以外の単結晶半導体膜を熱酸化することに
より得られる。この−、素子分離における熱酸化工程は
、半導体素子形成１ｊプロセスで最も時間の長い熱工程
であるため、シ・１．［リコン基枳上に既に素子が形成
さ筏ていた場合、□
”−上記熱工程によりその拡散層が広がる。このため、
下層のシリコン基板にチャネル長の短い素子を形成する
ことは困難であった。However, this type of method has the following problems. That is, when forming a semiconductor element such as a MOS transistor on an insulating film, element isolation of the semiconductor element is generally obtained by thermally oxidizing the single crystal semiconductor film outside the element forming region. This thermal oxidation step in element isolation is the longest thermal step in the semiconductor element formation process, so [If an element has already been formed on the silicon substrate, the diffusion layer will be expanded by the above thermal process. Therefore,
It has been difficult to form elements with short channel lengths on the underlying silicon substrate.
また、熱酸化を行わずに素子形成領域以外にＣＶＤ酸化
膜を埋込む低温プロセス型の素子分離方法も特殊な例と
して′蕊るが、この場合はプロセスが困難であり、更に
素子形成領域の側壁を流れるチャネル電流が発生し易い
。このため、単結晶半導体膜に形成する素子に良好な電
気特性を持たせることは困難であった。In addition, a special example is a low-temperature process element isolation method in which a CVD oxide film is buried in areas other than the element formation area without performing thermal oxidation, but in this case the process is difficult and the element formation area is Channel current flowing through the sidewalls is likely to occur. For this reason, it has been difficult to provide elements formed in single-crystal semiconductor films with good electrical characteristics.
本発明は上記事情を考慮してなされたもので、その目的
とするところは、熱酸化等の熱工程を用いることなく絶
縁膜上に形成する半導体素子の素子分離を行うことが・
でき、素子分離工程の簡略化をはかり得、且つ素子形成
領域の側壁を流れるチャネルリーク電流の発生のない優
れた電気特性を得られる半導体膜置の製造方法を提供す
ることにある。The present invention has been made in consideration of the above circumstances, and its purpose is to perform element isolation of semiconductor elements formed on an insulating film without using a thermal process such as thermal oxidation.
It is an object of the present invention to provide a method for manufacturing a semiconductor film device, which can simplify the element isolation process, and can obtain excellent electrical characteristics without generating channel leakage current flowing through the sidewalls of the element forming region.
本発明の骨子は、絶縁膜上に予めゲート電極となる導体
膜（金屈膜或いは半導体膜）を形成した：１後に、ゲー
ト電極となる導体膜上にゲート酵イ■゛ｔび単結晶半導
体ｎＩ影形成ることにあり、これ−゛により形成された
半導体素子はソース・ドレイン領域間の下にゲート酸化
膜を介してゲート電極が上にＭＯＳトランジスタを製造
する半導体膜置の−製造方沫において、前記絶縁膜上に
ゲート電極となる導体膜を形成したのち、この導体膜上
にゲート酸化膜を形成し、次いでこのゲート酸化膜上に
単結晶半導体膜を形成し、次いで素子形成領域以外の上
記単結晶半導体膜を除去し、次いで素子形成領域以外の
前記導体膜を選択的にエツチングして配線層を形成し、
しかるのちイオン注入により前記単結晶半導体膜中にソ
ース・ドレインとなる拡散層を形成するようにした方法
である。The gist of the present invention is to form a conductive film (golden film or semiconductor film) that will become a gate electrode on an insulating film in advance; The method of manufacturing a semiconductor film is to form a MOS transistor in which the gate electrode is placed above the source/drain region with a gate oxide film between the source and drain regions. After forming a conductor film to serve as a gate electrode on the insulating film, a gate oxide film is formed on the conductor film, a single crystal semiconductor film is formed on the gate oxide film, and then a region other than the element formation region is formed. removing the single crystal semiconductor film, and then selectively etching the conductor film other than the element forming region to form a wiring layer;
In this method, a diffusion layer that becomes a source/drain is then formed in the single crystal semiconductor film by ion implantation.
本発明によれば、絶縁膜上に形成する半導体素子の素子
分離には一切の熱工程を必要とせず、エツチングのみで
素子分離が達成される。このため、仮に下層のシリコン
基板上に素子が存在する場合においても該素子の拡散層
を広げることがなく、シリコン基板に微細なチャネル長
を有する素子を形成することが可能となる。また、絶！
！膜上の素子のソース・ドレインはゲート電極の上に位
置することになり、ゲート電極は素子形成領域の側壁と
接近することはない。このため、該側壁を流れるチャネ
ル電流が発生することはなく、絶縁膜上に形成する素子
に良好な電気特性を持たせることが可能となる。According to the present invention, element isolation of semiconductor elements formed on an insulating film does not require any thermal process, and element isolation can be achieved only by etching. Therefore, even if an element exists on the underlying silicon substrate, the diffusion layer of the element is not expanded, and it is possible to form an element with a fine channel length on the silicon substrate. Also, absolutely!
! The source and drain of the element on the film are located above the gate electrode, and the gate electrode does not come close to the sidewalls of the element formation region. Therefore, a channel current flowing through the sidewalls is not generated, and it is possible to provide an element formed on the insulating film with good electrical characteristics.
以下、本発明の詳細を図示の実施例によって説明する。 Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
嚇
第１図＜ａ）〜（ｈ）は本発明の一実施例に係ねる半導
体膜置の製造工程を示す断面図であり、第２図乃至第４
図はそれぞれ第１図（ｆ）〜（ｈ）に相当する斜視図で
ある。Figures 1A to 4H are cross-sectional views showing the manufacturing process of a semiconductor film device according to an embodiment of the present invention, and Figures 2 to 4
The figures are perspective views corresponding to FIGS. 1(f) to (h), respectively.
まず、第１図（ａ）に示す如く、面方位（１００）、比
抵抗５〜２０［０ｃｍ Ｊの単結晶シリコン基板（半導
体基板）１１上に第１のＣＶＤ酸化模１２を１［μｍ］
の厚さに堆積した。続いて、ＣＶＤ法を用い、ＣＶＤ酸
化、摸１２上に厚さ５０００ ［人］のタングステン膜
（導体膜）１３及び厚さ２５０［人］の第１の多結晶シ
リコン膜１４を順次堆積した。ここで、タングステン膜
１３は最終的にゲート電極及び配線層として用いるもの
である。その後、９００［”Ｃ］の温度で多結晶シリコ
ン膜１４を熱酸化し、第１図（ｂ）に示す如く厚さ５０
０［人］のゲート酸化膜１５を形成した。First, as shown in FIG. 1(a), a first CVD oxide pattern 12 is deposited on a single crystal silicon substrate (semiconductor substrate) 11 with a surface orientation (100) and a specific resistance of 5 to 20 [0 cm J].
deposited to a thickness of . Subsequently, a tungsten film (conductor film) 13 with a thickness of 5,000 [layers] and a first polycrystalline silicon film 14 with a thickness of 250[layers] were sequentially deposited on the pattern 12 by CVD oxidation using the CVD method. Here, the tungsten film 13 is ultimately used as a gate electrode and a wiring layer. Thereafter, the polycrystalline silicon film 14 is thermally oxidized at a temperature of 900 ["C] to a thickness of 50" as shown in FIG. 1(b).
A gate oxide film 15 of 0 [people] was formed.
次いで、第１図（Ｃ）に示す妃くゲート酸化膜１５上に
厚さ５０００ ［大コの第２の多結晶シリコンＩ！１１
６を堆積し、更にこの上に厚さ５０００［大コの第２の
ＣｖＤ酸化慢１７を堆積した。ここで、ｃｖｏｍ化躾１
７は、ビームアニール時に多結晶シリコン膜１６が蒸発
する現象を抑えるための保護膜となる。続いて、加速電
圧１２［ＫｅＶ］、ビーム電流２［ｍＡ］の電子ビーム
を用い、多結晶シリコン膜１６をビームアニールして単
結晶化した。Next, a second polycrystalline silicon I! layer with a thickness of 5000 mm is deposited on the gate oxide film 15 shown in FIG. 1(C). 11
A second CvD oxide film 17 was deposited on top of this to a thickness of 5000 m. Here, cvom training 1
Reference numeral 7 serves as a protective film for suppressing the phenomenon that the polycrystalline silicon film 16 evaporates during beam annealing. Subsequently, the polycrystalline silicon film 16 was beam-annealed to become a single crystal using an electron beam with an acceleration voltage of 12 [KeV] and a beam current of 2 [mA].
次いで、エツチング液としてＮ８４ ＦＦ）７液を用い
、第１図（ｄ）に示す如＜ＣＶＤＩｆ化ｙＡ１化合Ａ１
７、多結晶シリコン膜１６のビームアニールにより単結
晶化した単結晶シリコン躾１８をｎ出させた。続いて、
加速電圧３２０ ［ＫｅＶ］、ドーズは１×１０工３
［ｃｍ′２］のボロンイオン（Ｂ′″）を単結晶シリコ
ン膜１８に注入し、該膜１８をＰ−層にした。その後、
第１図（ｅ）に示す如く単結晶シリコン膜１８上に第３
のＣＶＤＭ化膜１９を厚さ２００ＯＣ人］堆積した。Next, using N84 FF7 solution as an etching solution, as shown in FIG.
7. Single crystal silicon film 18 made into a single crystal by beam annealing of polycrystalline silicon film 16 was exposed. continue,
Accelerating voltage 320 [KeV], dose 1×10 min3
[cm'2] of boron ions (B''') were implanted into the single crystal silicon film 18 to make the film 18 a P- layer.
As shown in FIG. 1(e), a third layer is formed on the single crystal silicon film 18.
A CVDM film 19 was deposited to a thickness of 200 cm.
次いで、第１図（ｆ）及び第２図に示す如く、ＣＶＤＩ
化膜１つ上に厚さ１［μｍ］のレジストを塗布し、この
レジストをパターニングして第１のレジストパターン２
０を形成した。続いて、リアクティブ・イオン・エツチ
ング法（ＲＩＥ法）を用い、レジストパターン２０をマ
スクとしてＣＶＤ１ａ化膜１９及び単結晶シリコンｐｌ
Ａ１８を選、率的にエツチング除去した。このとき、ゲ
ート酸化膜１５は単結晶シリコン膜１８をエツチングす
乞際のストッパーとなる。なお、この工程により、−素
子形成領域以外の部分が除去されたことになる。Next, as shown in FIG. 1(f) and FIG.
A resist with a thickness of 1 [μm] is applied on one of the chemical films, and this resist is patterned to form a first resist pattern 2.
0 was formed. Subsequently, using a reactive ion etching method (RIE method) and using the resist pattern 20 as a mask, the CVD 1a film 19 and the single crystal silicon PL
A18 was selected and etched away efficiently. At this time, the gate oxide film 15 serves as a stopper when the single crystal silicon film 18 is etched. Note that by this step, the portions other than the negative element formation region were removed.
次いで、レジストパターン２０を除去したのち、第１図
（Ｑ）及び第３図に示す如く、新たに第２のレジストパ
ターン２１を形成した。そして、レジストパターン２１
若しくはｃｖｏａ化膜１つで覆われていない部分におい
て、ゲート酸化膜１５及びタングステン膜１３をＲＩＥ
法により除去した。ここで、素子形成領域以外に残った
タングステン膜１３は、ゲート電極の引出しｇＡ域、つ
まり配線層となる。Next, after removing the resist pattern 20, a second resist pattern 21 was newly formed as shown in FIG. 1(Q) and FIG. 3. And resist pattern 21
Alternatively, the gate oxide film 15 and the tungsten film 13 are removed by RIE in the portions not covered with one cvoa film.
removed by method. Here, the tungsten film 13 remaining in areas other than the element formation region becomes a region gA for leading out the gate electrode, that is, a wiring layer.
次いで、第１図（ｈ）及び第４図に示す如く、同じレジ
ストパターン２１を用い、このレジストパターン２１を
マスクとしてＲＩＥ法によりＣＶＤＭ化摸１化合１９し
た。その後、加速電圧５０ ［ＫｅＶ］ 、 ドーズ巳
１Ｘ１０” Ｅｃｍ４〕のＡｓ“イオンを全面に注入
し、単結晶シリコン膜１８にＮ＋をの拡散層を形成した
。この拡散層は、〜１０Ｓトランジスタのソース・ドレ
インをなすものである。Next, as shown in FIG. 1(h) and FIG. 4, using the same resist pattern 21 and using this resist pattern 21 as a mask, the CVDM compound 19 was formed by the RIE method. Thereafter, As" ions were implanted into the entire surface at an acceleration voltage of 50 KeV and a dose of 1.times.10" Ecm to form an N+ diffusion layer in the single crystal silicon film 18. This diffusion layer forms the source and drain of the ~10S transistor.
これ以降は、レジストパターン２１を除去し、図示はし
ていないが全面にＣＶ Ｄ ｒｌｉ化膜を堆積し、゛′
通常のコンタクト開口工程及びＡＱ等からなる配′−形
成工程を順次行うことにより、Ｎチャネル型゛のＭＯＳ
トランジスタが完成することになる。After this, the resist pattern 21 is removed, and a CV Drli film is deposited on the entire surface (not shown).
By sequentially performing a normal contact opening process and a wiring formation process consisting of AQ, etc., an N-channel type MOS
The transistor will be completed.
かくして本実施例方法によれば、従来必要とされた素子
分離のための熱工程を省略することが可能となり、絶縁
膜１２上に形成する半導体素子の素子分離の際に、下層
のシリコン基板１１において再拡散が生じるのを未然に
防止することができる。このため、シリコン基板１１に
チャネル長の短い素子を形成しておくことができ、高集
積化にも有効である。また、素子形成領域の側壁を流れ
るチャネル電流を抑えることが可能となるので、絶縁膜
１２上に形成するＭＯＳトランジスタの素子特性向上を
はかり１ｑる等の利点がある。Thus, according to the method of this embodiment, it is possible to omit the conventionally required thermal process for device isolation, and when separating semiconductor devices formed on the insulating film 12, the underlying silicon substrate 11 It is possible to prevent re-diffusion from occurring. Therefore, elements with short channel lengths can be formed on the silicon substrate 11, which is effective for high integration. Furthermore, since it is possible to suppress the channel current flowing through the sidewalls of the element forming region, there are advantages such as improving the element characteristics of the MOS transistor formed on the insulating film 12.
なお、本発明は上述した実施例方法に限定されるもので
はない。例えば、前記ゲート電極となる導体膜はタング
ステンに限るものではなく、抵抗値が但く融点が高いも
のであればよい。一般的には、シート抵抗が５０［Ω］
以下のリン拡散型の多結晶シリコン膜や融点が１４１０
［’Ｃ］以上の高融点金属であれば用いることが可能で
ある。また、絶縁膜上に単結晶半導体膜を形成する方法
としては、非晶質若しくは多結晶の半導体薄膜をビ−ム
アニールするのが最も効果的であるが、実施例で説明し
た電子ビームの代りにレーザど−ムやイオンビーム等を
用いることも可能である。また、実施例ではＮチャネル
型のＭｏ８ トランジスタの製造方法を示したが、Ｐチ
ャネル型のＭｏＳトランジスタにも適用できるのは、勿
論のことである。Note that the present invention is not limited to the method of the embodiment described above. For example, the conductor film serving as the gate electrode is not limited to tungsten, and may be any material as long as it has a high resistance value and a high melting point. Generally, the sheet resistance is 50 [Ω]
The following phosphorus diffusion type polycrystalline silicon films and melting points are 1410
Any metal with a high melting point of ['C] or higher can be used. Furthermore, as a method for forming a single crystal semiconductor film on an insulating film, beam annealing of an amorphous or polycrystalline semiconductor thin film is the most effective method, but instead of using an electron beam as explained in the example, It is also possible to use a laser beam, ion beam, etc. Furthermore, although the method of manufacturing an N-channel type Mo8 transistor is shown in the embodiment, it goes without saying that the present invention can also be applied to a P-channel type MoS transistor.
ざらに、実施例では示していないが、シリコン基板上に
素子が既に形成されている場合においても、河谷問題な
く、絶縁膜上に〜＋ＯＳ ｔ−ランジスクを形成するこ
とが可能である。また、各層の膜厚。In general, although not shown in the examples, even when elements are already formed on the silicon substrate, it is possible to form the ~+OS t-range disk on the insulating film without any problem. Also, the thickness of each layer.
エツチング方法等は、仕様に応じて適宜変更可能である
。その他、本発明の要旨を逸脱しない範囲で、種々変形
して実施することができる。The etching method etc. can be changed as appropriate depending on the specifications. In addition, various modifications can be made without departing from the gist of the present invention.
第１図（ａ）〜（ｈ）は本発明の一実施例方法に係わる
半導体膜置の製造工程を示す断面図、第２図乃至第４図
はそれぞれ第１図（ｆ）〜（ｈ）に相当する構造を示す
斜視図である。
１１・・・単結晶シリコン基板（半導体基板）、１２・
・・第１のＣＶＤ酸化膜（絶縁膜）、１３・・・タング
ステン膜（導体Ｈ＞、１４・・・第１の多結晶シリコン
膜、１５・・・ゲート酸化膜、１６・・・第２の多結晶
シリコン膜、１７・・・第２のＣＶＤ酸化膜（保護膜）
、１８・・・単結晶シリコン膜（単結晶半導体膜）、１
９・・・第３のＣＶＤ酸化膜、２０・・・第１のレジス
トパターン、２１・・・第２のレジストパターン。
出願人 工業技ｉｆｉ院長 等々力 淫Ｑ
リＡ
ｏ
第３図
第４図
手 続 補 正 書 （方式）％式％
１、事件の表示
特願昭６１−９３２４８号
２、発明の名称
半導体膜置の製造方法
３、補正をする者
事件との関係 特許出願人
氏 名 工業技術院 次世代産業技術企画宮家電話 ０
３（５０１＞１５１１内線４６０１〜５４、補正命令の
日付FIGS. 1(a) to (h) are cross-sectional views showing the manufacturing process of a semiconductor film device according to an embodiment of the present invention, and FIGS. 2 to 4 are FIGS. 1(f) to (h), respectively. It is a perspective view showing the structure corresponding to. 11... Single crystal silicon substrate (semiconductor substrate), 12.
...First CVD oxide film (insulating film), 13...Tungsten film (conductor H>, 14...First polycrystalline silicon film, 15...Gate oxide film, 16...Second polycrystalline silicon film, 17... second CVD oxide film (protective film)
, 18... single crystal silicon film (single crystal semiconductor film), 1
9... Third CVD oxide film, 20... First resist pattern, 21... Second resist pattern. Applicant Industrial Technology ifi Director Todoroki InnoQ
Re A
o Figure 3 Figure 4 Procedures Amendment (Method) % formula % 1, Indication of the case Japanese Patent Application No. 1983-93248 2, Name of the invention Method of manufacturing semiconductor film device 3, Person making the amendment Related Patent Applicant Name Agency of Industrial Science and Technology Next Generation Industrial Technology Planning Miyake Telephone 0
3 (501>1511 extensions 4601-54, date of correction order
Claims (4)
ジスタを製造する半導体装置の製造方法において、前記
絶縁膜上にゲート電極となる導体膜を形成する工程と、
次いで上記導体膜上にゲート酸化膜を形成する工程と、
次いで上記ゲート酸化膜上に単結晶半導体膜を形成する
工程と、次いで素子形成領域以外の上記単結晶半導体膜
を除去する工程と、次いで素子形成領域以外の前記導体
膜を選択的にエッチングして配線層を形成する工程と、
次いでイオン注入により前記単結晶半導体膜中にソース
・ドレインとなる拡散層を形成する工程とを含むことを
特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device in which a MOS transistor is manufactured on an insulating film deposited on a semiconductor substrate, a step of forming a conductive film to serve as a gate electrode on the insulating film;
Next, forming a gate oxide film on the conductor film;
Next, a step of forming a single crystal semiconductor film on the gate oxide film, a step of removing the single crystal semiconductor film in areas other than the element formation area, and then selectively etching the conductor film outside the element formation area. a step of forming a wiring layer;
A method of manufacturing a semiconductor device, comprising the step of: forming a diffusion layer to become a source/drain in the single crystal semiconductor film by ion implantation.
の半導体膜或いは融点が１４１０［℃］以上の高融点金
属膜を用いたことを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。(2) The semiconductor according to claim 1, wherein a semiconductor film having a sheet resistance of 50 [Ω] or less or a high melting point metal film having a melting point of 1410 [°C] or more is used as the conductor film. Method of manufacturing the device.
以下の熱酸化膜を用いたことを特徴とする特許請求の範
囲第１項記載の半導体装置の製造方法。(3) The thickness of the gate oxide film is 1000 [Å]
A method of manufacturing a semiconductor device according to claim 1, characterized in that the following thermal oxide film is used.
ゲート酸化膜上に非晶質若しくは多結晶の半導体膜を堆
積したのち、レーザビーム或いは荷電ビームの照射によ
り該半導体膜を溶融・再結晶化することを特徴とする特
許請求の範囲第１項記載の半導体装置の製造方法。(4) In the step of forming the single crystal semiconductor film, an amorphous or polycrystalline semiconductor film is deposited on the gate oxide film, and then the semiconductor film is melted and recrystallized by irradiation with a laser beam or a charged beam. 2. A method of manufacturing a semiconductor device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9324886A JPS6354769A (en) | 1986-04-24 | 1986-04-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9324886A JPS6354769A (en) | 1986-04-24 | 1986-04-24 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6354769A true JPS6354769A (en) | 1988-03-09 |
| JPH0588543B2 JPH0588543B2 (en) | 1993-12-22 |
Family
ID=14077206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9324886A Granted JPS6354769A (en) | 1986-04-24 | 1986-04-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6354769A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02224255A (en) * | 1989-02-27 | 1990-09-06 | Hitachi Ltd | Thin film semiconductor device and manufacture thereof |
-
1986
- 1986-04-24 JP JP9324886A patent/JPS6354769A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02224255A (en) * | 1989-02-27 | 1990-09-06 | Hitachi Ltd | Thin film semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0588543B2 (en) | 1993-12-22 |
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