JPS635458A - Acknowledgment signal generating device - Google Patents

Abstract

PURPOSE:To guarantee an action of changing over a clock by generating an acknowledgment signal that does not depend on a system clock with respect to a command about the changeover of a clock. CONSTITUTION:If a command to request for the changeover of an input clock to be selected is transmitted from a CPU 1 to an LSI 10, a control part 3 transmits a register selecting signal and a write signal to a command register 4, and outputs an acknowledgment signal simultaneously. The register 4 is actuated by the write signal, and writes the command, and transmits a changeover control signal to a clock selection part 2. The selection part 2 selects, by the changeover control signal, one of input clocks. In such a case, the acknowledgment signal is continuously outputted during a period when the register 4 is writable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention selects one of a plurality of input clocks and uses the CPT in an LSI that operates with the selected clock.
J. above relates to an acknowledge signal generation device for read and write commands to registers inside an SI.

BACKGROUND ART FIG. 3 shows a block diagram of a conventional acknowledge signal generation device, in which IQ is an LSI having a plurality of input clocks. 1 is the CPU connected to LSllo
It is. 2 is a clock selection unit that selects one of a plurality of input clocks. 3 controls the registers inside the LS110 according to commands input from the CPU1,
CP that generates an acknowledge signal for the above command
This is a U command control unit. 4 is a command register. 5 is a synchronization register other than the command register.

In the conventional acknowledge signal generation device configured as described above, based on the command input from the CPU 1 to the LSI 10, the CPU command control unit 3 outputs a register selection signal specifying the register to be selected. Alternatively, reading and writing of the synchronization register 6 is performed in synchronization with the system clock. At the same time, CPU1
In response, an acknowledge signal is returned from the CPU command control unit 3 in synchronization with the system clock. Note that the system clock is selected from among a plurality of input clocks by the clock selection section 2 based on the state of the command register 4.

In the above configuration, since the command register 4 operates in synchronization with the system clock, the pulse width of the system clock at the moment when the input clock to be selected is switched may become narrower, and the cono pulse width may become narrower than the writing of the command register 4. If the pulse width is less than the required pulse width, the state of the command register 4 will not change and the clock switching will be unsuccessful. - On the other hand, an acknowledge signal for writing to the command register 4 is generated in the CPU command control unit 3 in synchronization with the system clock, so even if writing to the command register 4 fails, an acknowledge signal is returned and clock switching is executed. The problem was that it was not possible.

FIG. 4 is an explanatory diagram illustrating the above problem.

Now, input the control signal shown in &~C in the figure from CPU1 to LSllo, and select the input clock by CK1 in d in the figure.
Let us assume that we want to switch from CK2 to CK2 in e of the same figure. At this time, the data marked & in the figure is R, which instructs the selection of the command register 4.
After the logic levels of the GSL (b in the figure) signal and the WT (C in the figure) signal that instructs writing to register 4 both become LOW (time t1), the rising edge of the system clock (time t
2) is written to the command register 4. The command register 4 performs clock switching control based on input data so that the system clock is at time t.

Switches to CK2 at . However, at this time, the system clock rises at time t2 and falls at time t5, as shown in FIG. Therefore, the switching of the input clock is also unsuccessful, and the time t4
OKl becomes the system clock again. The figure shows the system clock. - On the other hand, the acknowledge signal is returned in synchronization with the system clock as shown in g in the same figure, so the WT goes HI at the falling edge of human CK at time t.
The signal becomes GH level (time t5), and clock switching becomes impossible.

Problems to be Solved by the Invention Since the command register operates in synchronization with the system clock, the pulse width of the system clock may become narrow at the moment when the input clock to be selected is switched.
If this pulse width becomes less than the pulse width required to write to the command register, the state of the command register will not change.
Clock switching is unsuccessful.

Means for Solving the Problems In order to solve the above problems, the present invention includes a control unit that guarantees writing of data to the command register, and relies on the system clock for reading and writing to the command register. This is an acknowledge signal generation device that outputs an acknowledge signal in synchronization with the system clock for reading and writing of registers other than the command register.

According to the above-described configuration, when the CPU gives a command to switch the input clock of the LSI, the above command is written to the command register by a control signal sent from the CPU command control section, and the input clock is switched off. Change. At the same time, an acknowledge signal for the above command is output from the CPU command control section without depending on the system clock, and the switching of the input clock is completed.

Example .

FIG. 1 shows a block diagram of an acknowledge signal generation device in an embodiment of the present invention. Note that elements common to those in FIG. 3 are given the same numbers.

The operation of the acknowledge signal generation device of this embodiment will be described below. In FIG. 1, the command requesting switching of the input clock to be selected from the CPU 1 is LS.
When the command is sent to the command register 4, the CPU command control unit 3 inside the LS 110 sends a register selection signal and a write signal to the command register 4 in order to write the command to the command register 4, and at the same time starts outputting an acknowledge signal. The command register 4 is operated by the write signal, writes the command, and sends a switching control signal to the clock selection section 2. The clock selection section 2 selects one of the input clocks according to the switching control signal. At this time, the acknowledge signal is output while the command register 4 is writable. Regarding access to the synchronization register 6, an acknowledge signal is returned in synchronization with the system clock as before.

FIG. 2 is an explanatory diagram of the operation of this embodiment at the time of clock switching. In FIG. 2, the register selection signal RGSL (
Writing to the command register 4 is possible during a period when both the write signal WT (b) in the figure and the write signal WT (c) in the figure are at LOW level.

The clock switching command is written to the command register by the falling edge of WT at time T, and the input clock to be selected at time T2 changes from CK1 (d in the figure) to CK2 (
The display switches to e) in the same figure. Therefore, the system clock SCK becomes as shown in f' in the figure. - direction actu ridge signal A
CK is output from time T1 to time T4, as shown in g' in the figure, according to the logic between RGSL and WT.

As described in detail, according to the present invention, in response to a command related to clock switching, an acknowledge signal that does not depend on the system clock is generated, and clock switching operation can be guaranteed. The effect is significant.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of an acknowledge signal generation device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the same embodiment, FIG. 3 is a block configuration diagram of a conventional acknowledge signal generation device, and FIG. 4 is an explanatory diagram of the operation of the conventional example. 1...CPU, 2...Clock selection section, 3...CPU command control L 4...
・Command register, 6...Synchronization register, 1
0... Name of LSI0 agent Patent attorney Toshio Nakao and 1 other person ＼r −−−−−−−−−−1−
−−−−−”'−”−T!

Claims (1)

[Claims] A command register that selects one of a plurality of externally input clocks and operates in synchronization with the selected system clock, and holds a command related to clock switching input from the CPU; It includes a clock selection section that switches the input clock based on the output of the register, and a control section that controls the operation of the command register, and acknowledges read and write commands from the CPU to the synchronization register in synchronization with the system clock. An acknowledge signal generation device that outputs a signal and outputs an acknowledge signal without depending on a system clock for read and write commands to the command register.