JPS59202531A - Unit for processing information capable of changing machine cycle time - Google Patents

Abstract

PURPOSE:To eliminate the need for the change in hardware even if the machine cycle time is changed by deciding the machine cycle number required to maintain a prescribed relation of time to supervise the elapsed machine cycle numbers. CONSTITUTION:A counter circuit 23 receives the control of a counter control circuit 22 to count the number of clock pulses generated in a period of a reference pulse. Further, when the machine cycle time is TB, since the count value shows an NTB, the reference value of a comparison circuit 24 is set in advance to the NTB. When the machine cycle time reaches the TB or over, an output of the comparison circuit 24 goes to 1, then an AND gate 27 is turned on at a cycle number supervising circuit 25 and the machine cycle number for skew compensation is selected to 2.5. On the other hand, when the machine cycle time is less than the TB, the machine cycle number is selected to 3.5 by an AND gate 26.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a clock-synchronized information processing device, and particularly to an information processing device in which machine cycle time can be changed.

[Background of the invention]

Users' expectations regarding the processing power of recent electronic computer systems
In order to cope with diversifying needs, we first prepared a central processing unit (hereinafter referred to as a CPU) with the most advanced processing power, and based on this CPU, we developed CPUs with different levels of processing power. A method of expansion has begun to be adopted. In this case, it is necessary to add the processing capacity of the CPU to each value, but as a means of doing so, machine cycle
There is a way to change the time. However, when adopting this method, the following problems need to be solved. In other words, there are parts of the CPU that are subject to time constraints,
In such parts, it is necessary to exchange signals at predetermined times. Clock synchronous CPU
In order to create these time relationships, it is sometimes done to count the number of machine cycles that have passed. For this reason, when the machine cycle time changes, the initially set number of machine cycles may deviate from the predetermined time relationship. In other words, as the machine cycle time increases and decreases, the CPU becomes unable to comply with the minimum and maximum time regulations, respectively.
Occurs in

In order to solve this problem, conventional methods have been to change the counter setting value by changing the connection of the gate circuit on the package according to the change in the machine cycle time, and to calculate the number of machine cycles that should be counted. For this reason, there was a drawback that the machine cycle time could not be easily changed, and furthermore, this was a problem when attempting to implement LSI.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide a means for automatically maintaining a predetermined time relationship even if the machine cycle time changes without making any changes to the hardware. Our goal is to provide the following.

[Summary of the invention]

The present invention includes a cycle time identifying means that identifies a set machine cycle time value and outputs a predetermined output, and a machine cycle required to maintain a predetermined time relationship by specifying the cycle time identifying means. By providing a cycle number monitoring means for determining the number of machine cycles and monitoring the number of elapsed machine cycles, even if the machine cycle time is changed, the machine cycle time can be determined in advance without changing the hardware. It is characterized by maintaining a fixed time relationship.

[Embodiments of the invention]

FIG. 1 shows an example of the configuration of an electronic computer system that implements the present invention.
, a CPU consisting of an arithmetic processing unit 2 (hereinafter referred to as BPU) and an input/output processing unit 8 (hereinafter referred to as IOP), a magnetic disk unit 4 (hereinafter referred to as DK) and a magnetic tape unit 5 (hereinafter referred to as MT). An I10 device such as the following is connected. 10P8 includes a plurality of channel devices 6 (hereinafter referred to as CH), and the valley CH controls data transfer between the I10% station and the MSI according to commands from the BPU2.

In a large system, the processing power of the CPU can be increased by changing the machine cycle time]
can be controlled. In other words, by increasing the syncycle time, in the MSI, the data transfer ability decreases due to the increase in the time required to access the memory, and in the BPU2, the time required to access the memory decreases, and in the BPU2, the time required to access the memory increases. In P8, there will be a decrease in the overall data transfer capacity due to an increase in the time spent on internal processing and a decrease in the data transfer capacity between MSI, so the processing capacity as a C and PU will be reduced. Control is OT
It is Noh.

On the other hand, even if the processing power of the CPU changes, there are some places that require a certain amount of processing power. As an example, CH
There is control of the I10 interface between '6 and I) I10 devices such as K4 and I'vlT5.

FIG. 2 shows the exchange of I10 interface signals when transferring data from CH6 to the I10 device. I10
When making a request for data transfer, the device
Using e-In and Data-In signals alternately, CH
A data transfer request is made to 6. When CH6 receives a data transfer request, it sends the data to be transferred on BUS-Out, and after a certain period of time (referred to as skew compensation time), 5erv 1ce-I
For n, 5service-Out, Data-
In response to In, a Data-Out response is made. ■10
Upon receiving the response, the duty officer withdraws the data transfer request after receiving the data on BUS-0ut, and in any case, returns the data transfer request to 5service-In.
The above operation will be repeated using and Data-In alternately.

Here, in the I10 wheel alignment of DK4 and MT54, data transfer within a certain time interval is determined by the relationship between the recording density of the recording medium and the relative speed between the recording medium and the read/write head. It is necessary to do so. What is this condition?
11I! Otherwise, data will not be recorded correctly. Therefore, even if the machine cycle time is changed, this time relationship should remain within the specified range.
(This means that the sum of Ta, T6, and 'ro in FIG. 2 must be less than or equal to a certain value.

Figure 3 shows the clock pulses of the CPU implementing the present invention, and Figure 4 shows part of the logic circuit that uses these clocks to create the aforementioned skew compensation time. , FIG. 5 is a time chart diagram illustrating the operation of the logic circuit shown in FIG. 4.

In Figure 4, the 5erv sent from the I10 device
The ice-In signal is synchronized by the synchronization circuit 10 with the clock of the CPU shown in FIG.
When the In signal rises and falls, a signal corresponding to one machine cycle is outputted (Fig. 5 (A), (→)).

Among these, the rising signal is used to set the data to be transferred in the register 15 (only 1 bit is shown in Figure 4).
(14th flop)
(see Figure 5)). The output of the flip-flop 14 is input to the counter 16 to start a counting operation (see FIG. 5). The output of the counter 16 is a predetermined value (
When the binary number in FIG. )) At the same time, the flip-flop 14 is reset through the OR gate 13 (fifth
In the figure)). When the solitub flop ■4 is reset,
The output of counter 16 is reset to zero. 5erv
5service -I by ice -0ut signal
When the n signal is withdrawn, a falling signal is output from the differentiating circuit 11, and the flip-flop addition is reset through the tJR gate 19 (FIG. 5(g)).
The service -Out signal is also withdrawn.

As described above, a series of time-related controls as shown in FIG. 2 are performed when data is transferred from the CH to the 110 device.

In this case, the skew compensation time is changed by changing the final value of the count set in the cycle number monitoring circuit 17. - For example, by connecting between A and C or between B and C of the switch SW, the skew compensation time is 3, 5 times and 2, 2 times the machine cycle time, respectively.
It can be set to 5 times the value.

Next, in the logic circuit constructed in this manner, changes in connections between A and C and between B and C due to changes in machine cycle time will be explained. As can be seen from Figure 2, C)(
When connecting 110 devices with R, megabytes and 7 seconds of data transfer V-), with 6 turning once to and from the I/'0 device, the relationship between R and Ta, Tb, and T is as follows. It is necessary to satisfy the formula.

1000 /R>'I', +Tb +'rc (77 seconds) Ta and T. includes the propagation delay time due to the ■10 interface cable for connecting the CH6 and I10 devices and the processing time within the CH6 and I10 devices, and the maximum allowable cable length is usually specified for the I10 interface cable. Ta and T. The sum is less than a certain value. However, the relationship between R and Tb can be expressed by the following equation.

R< zoooo / ('I't, + C)'rb>
1000 /R, - In Nico, Ta + T. , and the above relationship is a constant 1
Direct. Tb is the above-mentioned skew compensation time, and the minimum time to be secured is determined taking into consideration the variation in propagation delay time of the circuit system.21. Ru.

FIG. 6 shows the relationship between R and Tb. 'rb is a multiple value of the machine cycle time, which similarly increases by 1 as the machine cycle time increases or decreases. #I minute A-A'
and a-a' indicate changes in skew compensation time and data transfer rate due to changes in machine cycle time when the number of machine cycles to ensure skew compensation time is 3.5, and similarly the line segment B-d and bb' show the changes when the number of machine cycles was set to 5.

As is clear from Fig. 6, in order to satisfy the minimum skew compensation time, if the number of machine cycles to secure the skew compensation time is 3.5ζ, If it is set to 2.5, it must be TB or more. Also, I10
In order to keep the data transfer rate with the device above Rmin, if the number of machine cycles is 3.5, it should be below TA',
If the number of machine cycles is 20.5, it must be less than 'r'. From these reasons, the range in which the machine cycle time can be changed is 3.
As long as there are two, 5 and 2.5, it is between TA and Td. In addition, in order to satisfy both the data transfer rate Rmin and the minimum skew compensation time, if the machine cycle time is greater than or equal to TA and less than or equal to 1'A', the number of machine cycles should be set to 3.5,
'IIJ3 or more, T' In the following cases, it must be set to 265, and accordingly, it is necessary to change the connection between A-0 and B-0 of the switch SW in the cycle number monitoring circuit 17 in Fig. 4. Figure 7 is an example of a skew compensation circuit implementing the present invention, and in order to automatically satisfy the above requirements, a cycle is created that identifies the set machine cycle time and outputs a predetermined output. A time identification circuit 21 and a cycle number monitoring circuit 5 that determines and monitors the necessary and sufficient number of machine cycles required for skew compensation based on the output thereof are shown.The cycle time identification circuit 21 includes a counter control circuit z2, a counter circuit, and a comparison circuit. The cycle number monitoring circuit section corresponds to the circuit 17 in FIG.

Counter control circuit 22 in cycle time identification circuit 21
controls the counter circuitry in response to a reference pulse with a fixed period that is sufficiently larger than the machine cycle time. In this embodiment, a reference pulse prepared for a time mechanism that displays the date and time in the CPU is used as this fixed-cycle reference pulse. Under the control of the counter circuit 1 and the counter control circuit 4, the number of clock pulses ('r o ) generated within the period of the reference pulse is counted.

If the machine cycle time is TB, the count value is N
In the case of 'rB,'rA', the count value indicates NTd.

These count values are sent to a comparator circuit and compared with a reference value. By setting the reference value to NTB in advance, the comparator circuit sets the output to "1" when the count value is less than or equal to NTk3. When the output of the comparator circuit becomes "1", that is, when the machine cycle time exceeds TB, the cycle number monitoring circuit δ outputs the ANI) gate 27.
is turned on, and 2.5 is selected as the number of machine cycles for skew compensation. If the machine cycle time is less than 18, 3.5 is selected as the number of machine cycles for skew compensation by AND game 26, and the above-mentioned requirements can be satisfied.

FIG. 8 shows an example of a skew compensation circuit embodying the present invention. In this method, a switch circuit 32 is provided on a logic board (9) to which an oscillator 31 for generating clock pulses is attached, and the switch circuit 32 is manually set to a predetermined value according to the value of the oscillation frequency of the oscillator 31. It is. This method is the seventh
It has the feature that it can be realized with less hardware than the embodiment shown in the figure. The embodiment shown in FIG. 7 is characterized in that it does not require any manual intervention.

〔Effect of the invention〕

According to the present invention, even if the machine cycle time is changed, a predetermined time relationship can be automatically maintained without making any changes to the dock air.

Although the embodiment has been described only with reference to the I10 interface, it can also be used to control the refresh interval in the main memory using dynamic ItAM. That is, in order to maintain the highest processing power of the CPU, it is desirable to minimize the occurrence of the main memory being in use due to refreshing. For this purpose, the machine cycle time should be kept at a minimum refresh time interval or the maximum allowable limit (and as the machine cycle time increases, the refresh minimum valley time may be exceeded). This results in information loss.The present invention can also be used in such cases.

[Brief explanation of the drawing]

Is Figure 1 an example of a lecture on computer systems? 2 is a diagram showing the time relationship of the I10 interface signal in FIG. 1, FIG. 3 is a diagram showing clock pulses, FIG. 4 is a diagram showing the skew compensation circuit before implementation of the present invention, and FIG. is a timing diagram for explaining the operation of FIG. 4, FIG. 6 is a diagram showing the relationship between machine cycle time, skew compensation time, and data transfer rate, and FIGS. 7 and 8 are skew compensation diagrams in which the present invention is implemented. FIG. 2 is a diagram showing an example of a circuit. 16... Counter, 21... Cycle time identification circuit, 5... Cycle number monitoring circuit. Fang 4 Figure 5 Figure 1-7 Shinsui 2 Runuihe Figure 7 1

Claims (1)

[Claims] (1) In an information processing device in which the machine cycle time can be changed, there is provided a cycle time identification means for identifying the set value of the machine cycle time, and a predetermined time relationship based on the sliding foot of the identification means. It is equipped with a cycle number monitor stage that determines the number of machine cycles required to maintain the machine cycle time and monitors the number of machine cycles that have passed, and maintains a predetermined time relationship even if the machine cycle time is changed. An information processing device characterized in that the parts that need to be processed are controlled in such a manner.