JPS6353659A - Image memory device - Google Patents

Abstract

PURPOSE:To freely allocate physical memories in a logical address space for the unit of blocks and to use the memories efficiently by providing an address conversion table set by the output of a computer. CONSTITUTION:For operating an image memory device, a memory address signal to access an address bus 5 is outputted. In the case of writing, write data is outputted to a data bus 16, and a memory write command 11 is made enable. Write plane specification data is previously set to a register 10 due to the output of the computer. An RAS.CAS signal generator circuit 13 makes enable signals RAS and CAS in a layer specified by the reading of the register 10, activates DRAMs 1-4, and writes data on the data bus at a specified address. In the case of reading, a memory read command signal 12 made enable. A multiplexer 15 selects one plane and outputs its data on the data bus.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application in M Industry) The present invention relates to various image display devices such as bitmap displays, graphic displays, and workstations. In an image memory device that stores image information having various capacities.

The present invention relates to an image memory device configured to allow physical memory to be freely allocated in block units within a memory address space.

(Prior Art) When displaying different image data in multiple windows on a display, it is necessary to have an image memory (hereinafter referred to as VM) that stores one image data in addition to a frame buffer that stores data to be displayed on a CRT display device. There is. When performing multi-window display, parts of several different pieces of data stored in the VM are cut out into rectangular areas, copied to a frame buffer, and displayed.

Normally, one window on this VM corresponds to one virtual terminal, so when a display device is operated in a multitasking environment, window creation and window deletion occur dynamically. Each window has a different size and different depth information, and by repeatedly creating and deleting such windows, the arrangement of image data stored in the VM in the address space becomes disordered and becomes extremely complicated. As a result, the limited capacity of VMs cannot be used effectively.

This method has the disadvantage that memory is wasted and the performance of the entire device is degraded.

(Problems to be Solved by the Present Invention) In order to solve these drawbacks, the present invention replaces the correspondence between the memory space and the physical memory, which was fixed in conventional image memory devices, by using an address set by computer output. By providing a conversion table, it is possible to dynamically allocate each layer for each layer, and even when image data of different sizes and depth information is stored and deleted in a timely manner, efficient memory usage is possible. The present invention provides an image memory device with a memory management scheme that enables two image memory devices to improve performance.

(Example) An embodiment of the present invention shown in the drawings will be explained in detail below.

FIG. 1 shows a block diagram of an embodiment of the present invention. 1
, 2, 3.4 are four-layer image memory planes each consisting of 16 dynamic reference random access memories (hereinafter referred to as DRAMs) each having a word length of 1 bit×IM word. 5 is an address bus that outputs an address when an external device (not shown) reads or writes the memory.

Consists of 20 AO-A19. 6, 7, and 8.9 are address conversion tables that are a feature of the present invention.
It consists of a 56-byte static random access memory (hereinafter referred to as SRAM), and the upper 8 bits of address bus 5 (A19 to A12) are input to the entry address of the SRAM, and the table-converted 8-bit data is input. is input as a translation address to the upper address of the memory plane of each layer. Lower 1 of address bus 5
2 pins 1-(AIl to AO) ld are directly input to the lower addresses of each memory brain. 10 is a computer (not shown), write plane designation TC set from the output), 1
．． 2 is a memory read command signal (MRDC).

13 generates the DRAM RAS signal and CAS signal)
<ASCAS signal generation circuit. 14 is a 16-bit bus driver, and 15 is a multiplexer.

To operate an image memory device configured in this way,
A memory address signal for accessing the address bus 5 is output, and in the case of writing, write data is transferred to the data bus and the memory write command signal MWTCII is enabled. At this time, write plane designation data is set in advance in the 4-bit register 1° by a computer output (not shown). The RAS/CAS signal generation circuit 13 activates the DRAM by enabling the RAS signal and CAS signal of the layer specified by the value of the register 10, and stores the data on the data bus at the specified address. Furthermore, in the case of reading, the memory read command signal MRDC:1.2 is enabled.

As to which plane's data is to be read, one plane is selected by the multiplexer 15 and the data is output onto the data bus.

As mentioned above, memory planes 1, 2, and 3.4 are composed of 1.6 1Mbit DRAMs per layer, so 1
The number of sear address signal lines for 1M words per layer is 220.
= 20 books from IM. Of the 20 external addresses AO-A19, the lower 12 bits (AO-A1
1) is input as is to the lower address of DRAM, but ``2nd place 8 pinos'' (A12 to A19) are input to the address consisting of 256 bytes of SRAM? Table 6.
7, 8.9 The entry address has been filled out. Therefore, since 212 = 4K words, the memory of 1M words is divided into 4 and 28 = 256 blocks with each word as 1 block, and +-'f: 4 is the logical address from the outside in word units and the physical address of the real memory. Conversion becomes possible.

FIG. 2 is a diagram showing the correspondence between logical addresses and physical addresses. Since the number of address signal lines for both the logical address and the physical address is less than 20, the address space is an IM word.

For example, as shown in Figure 2, address 6-0H of the address conversion table is 02H, 01 address is OOH, 02H.
Assuming that the address is OIH and the address 03H is F F H, the external device is set to 00000H.
When outputting the logical address of the address, the upper 8 bits OOH selects the OOH address of the address conversion table, so data 02H stored at address 00H is output as the exchanged upper address. , the physical address 02000H is accessed. Similarly, when the logical address 03000H is output, the upper address is converted to the same FFH at address 03H in the conversion table,
FF0OOI (address is accessed.

Therefore, physical memory can be freely arranged in a logical address space of 1M words for each layer, with 4 words as one block.

This arrangement change can be done quickly by rewriting the memory contents of 256 bytes per layer using computer output.

Next, the actual memory usage method will be explained in detail.

As an example, consider the case of four layers of memory with four blocks per layer, as shown in FIG. It is now assumed that the address translation table has been initialized as shown in FIG. Task A now has a request to generate a υ window, and after allocating 0000H to 100OH of plane O, plane 0 is assigned to task B's window generation request.
If 1000H to 2ooOH (734th layer) are allocated, the data arrangement in the memory will be as shown in FIG. Next, when task C requests an area for three block layers, in the conventional method, even though there was sufficient free memory capacity, only two blocks could be secured because the addresses were not consecutive. 2. If the address conversion table is rearranged as shown in Figure 5 using the memory device of the present invention, even if the data of C is stored discontinuously in blocks in the address space of the physical memory, it can be accessed from the outside. It can be treated as being stored in a contiguous area in the logical address space, so if there is enough free memory capacity, the necessary area can be secured in the contiguous logical address space. can be used effectively.

(Effects of the Invention) As explained above, according to the present invention, physical memory can be freely allocated in blocks within the logical address space, and image data having different sizes and depth information can be stored and erased repeatedly. This has the advantage of making it possible to effectively use the limited capacity of image memory even when

[Brief explanation of the drawing]

Figure 1 is a professional circuit diagram showing one embodiment of the invention;
3 and 5 are graphs showing the correspondence between logical addresses and physical addresses. and FIG. 4 are diagrams showing the arrangement of data in memory space. 1-4...Plane O-3, 6-9...Address conversion table, 10...Register, 13...RA, 5-
CAS signal generation circuit, 15...Multiplexer Atsushi 3 Figure 0 and 7 Figure 5

Claims (1)

[Claims] In an image memory device that is configured with multiple layers in the depth direction and is equipped with an address conversion table that converts addresses for each layer, the address space of the memory can be changed for each layer by rewriting the contents of the address conversion table using computer output. An image memory device characterized in that it is configured such that physical memory can be freely allocated in block units within the image memory device.