JPS635237Y2 - - Google Patents
Info
- Publication number
- JPS635237Y2 JPS635237Y2 JP1982173735U JP17373582U JPS635237Y2 JP S635237 Y2 JPS635237 Y2 JP S635237Y2 JP 1982173735 U JP1982173735 U JP 1982173735U JP 17373582 U JP17373582 U JP 17373582U JP S635237 Y2 JPS635237 Y2 JP S635237Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- wiring pattern
- sealing
- semiconductor device
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17373582U JPS5977231U (ja) | 1982-11-16 | 1982-11-16 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17373582U JPS5977231U (ja) | 1982-11-16 | 1982-11-16 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5977231U JPS5977231U (ja) | 1984-05-25 |
| JPS635237Y2 true JPS635237Y2 (enrdf_load_stackoverflow) | 1988-02-12 |
Family
ID=30378401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17373582U Granted JPS5977231U (ja) | 1982-11-16 | 1982-11-16 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5977231U (enrdf_load_stackoverflow) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2575331B1 (fr) * | 1984-12-21 | 1987-06-05 | Labo Electronique Physique | Boitier pour composant electronique |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5413966A (en) * | 1977-07-01 | 1979-02-01 | Nippon Electric Co | Substrate for multiilayer wiring |
| JPS5471572A (en) * | 1977-11-18 | 1979-06-08 | Fujitsu Ltd | Semiconductor device |
| JPS5731165A (en) * | 1980-07-31 | 1982-02-19 | Fujitsu Ltd | Semiconductor device |
-
1982
- 1982-11-16 JP JP17373582U patent/JPS5977231U/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5977231U (ja) | 1984-05-25 |
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