JPS5413966A - Substrate for multiilayer wiring - Google Patents

Substrate for multiilayer wiring

Info

Publication number
JPS5413966A
JPS5413966A JP7934577A JP7934577A JPS5413966A JP S5413966 A JPS5413966 A JP S5413966A JP 7934577 A JP7934577 A JP 7934577A JP 7934577 A JP7934577 A JP 7934577A JP S5413966 A JPS5413966 A JP S5413966A
Authority
JP
Japan
Prior art keywords
multiilayer
wiring
substrate
multiilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7934577A
Other languages
Japanese (ja)
Inventor
Hisao Kanai
Masaaki Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7934577A priority Critical patent/JPS5413966A/en
Publication of JPS5413966A publication Critical patent/JPS5413966A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
JP7934577A 1977-07-01 1977-07-01 Substrate for multiilayer wiring Pending JPS5413966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7934577A JPS5413966A (en) 1977-07-01 1977-07-01 Substrate for multiilayer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7934577A JPS5413966A (en) 1977-07-01 1977-07-01 Substrate for multiilayer wiring

Publications (1)

Publication Number Publication Date
JPS5413966A true JPS5413966A (en) 1979-02-01

Family

ID=13687304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7934577A Pending JPS5413966A (en) 1977-07-01 1977-07-01 Substrate for multiilayer wiring

Country Status (1)

Country Link
JP (1) JPS5413966A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130453A (en) * 1981-02-06 1982-08-12 Nec Corp Thin film circuit device
JPS5982750A (en) * 1982-11-02 1984-05-12 Nec Corp High density ceramic package
JPS5977231U (en) * 1982-11-16 1984-05-25 京セラ株式会社 semiconductor equipment
JPS59204258A (en) * 1983-05-06 1984-11-19 Nec Corp Chip-processed microwave band integrated circuit
JPS6030155A (en) * 1983-07-28 1985-02-15 Toshiba Corp Module of hybrid integrated circuit
JPS60110143A (en) * 1983-11-18 1985-06-15 Fuji Xerox Co Ltd Large area semiconductor device
JPS62248242A (en) * 1986-04-22 1987-10-29 Matsushita Electronics Corp Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130453A (en) * 1981-02-06 1982-08-12 Nec Corp Thin film circuit device
JPS5982750A (en) * 1982-11-02 1984-05-12 Nec Corp High density ceramic package
JPS5977231U (en) * 1982-11-16 1984-05-25 京セラ株式会社 semiconductor equipment
JPS635237Y2 (en) * 1982-11-16 1988-02-12
JPS59204258A (en) * 1983-05-06 1984-11-19 Nec Corp Chip-processed microwave band integrated circuit
JPS6030155A (en) * 1983-07-28 1985-02-15 Toshiba Corp Module of hybrid integrated circuit
JPS60110143A (en) * 1983-11-18 1985-06-15 Fuji Xerox Co Ltd Large area semiconductor device
JPS62248242A (en) * 1986-04-22 1987-10-29 Matsushita Electronics Corp Semiconductor device

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