JPS6351381B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit in which power supply wiring with low direct current resistance and inductance can be provided without impairing the freedom of arrangement and wiring of logical functional elements.

As semiconductor integrated circuits (LSI) become larger in scale, much effort is required to design mask patterns for functional elements and wiring from logical connection information, so-called artwork design. Recently, automatic artwork design using computers has been considered, and the master slice method and building block method are attracting attention as LSI methods suitable for this automatic design.

In the master slicing method, a large number of general-purpose cells consisting of active elements such as transistors and passive elements such as resistors are formed in advance in a matrix on a single semiconductor chip, and the cells are divided according to the developed product (specifications of circuit functions). A wiring mask is created to connect the elements within the general purpose cell, thereby achieving the desired logic function. The logic functions realized by these cells are then connected to complete a desired semiconductor integrated circuit.

In addition, in the building block method, for one logical function, logical cells having artwork data to realize that function are registered in a cell library, and these are selected and combined as appropriate according to logical connection information. A semiconductor integrated circuit with a desired circuit function is realized by arranging the logic cells and wiring between the logic cells.

What these systems have in common, however, is that they include an active element area in which active elements realizing a logic function are formed on a semiconductor chip, and a wiring area in which a wiring track is formed to connect the input and output of the logic function. It is a point. The wiring track is a matrix-like line virtually set with standardized widths and intervals, and wiring for connecting inputs and outputs of the logic function is provided on this wiring track. Another common feature is that a power supply line and a ground line for supplying power to each active element are provided to pass through the active element area.

In any of these methods, or in other similar methods, the following problems have arisen as LSIs become larger and smaller. This problem will be explained using a semiconductor integrated circuit realized by the master slice method as an example.

FIG. 1 shows an example of a connected cell type LSI in which general-purpose cells (logical function cells) 1 are arranged vertically to form a cell row 2. The cell row 2 constitutes one active element area 3. ing. A wiring region 4 is defined between the active element regions 3, and within the wiring region 4, wiring tracks are set in a lattice shape at standardized intervals. A signal line 5 connecting each general-purpose cell 1 is arranged on this wiring track. The signal lines 5 are provided to interconnect the general-purpose cells 1 according to the logical function to be realized on the semiconductor integrated circuit. Further, in this example, a power supply line 6 and a ground line 7 are respectively arranged in the column direction of the cell row 2 through the active element region 2 to supply power to each general-purpose cell 1. Note that 8 in the figure indicates a semiconductor pellet.

However, as LSIs become larger and smaller, the power line 6 and ground line 7 become narrower, thinner, and longer.
For this reason, the resistance of the power supply line increases and the drop in power supply voltage cannot be ignored. For example, specific resistance ρ=
Power line 6 made of 2.83×10 ^-6 Ω・cm Al material
If the width is 2μm, the thickness is 0.8μm, and the length is 10mm,
Its DC resistance is 117Ω. Even if this is connected to the bus bar 9 at two locations, the top and bottom, if a logic function that consumes 10 mA of current is implemented in the center of the chip, a power supply voltage drop of 0.885 V will occur. Such a power supply voltage drop not only reduces the speed of circuit operation but also causes malfunction. Furthermore, the circuit is C-
If it is a MOS configuration, it can also be a cause of latch-up phenomenon.

Furthermore, the inductance of the power line as described above is also considerably large. For example, the above specifications
With Al wiring, an inductance of about 13nH occurs with a length of 10mm. This inductance causes a current change of 10 mA per 1 ns (di/dt=
10 ⁷ A/sec), it will generate a spike voltage of 0.13V across it. This spike voltage also causes circuit malfunctions and latch-up phenomena, which are problems that must be improved.

In contrast, conventionally, as shown in FIG. 2, a power line 6 and a ground line 7 were also provided in a direction perpendicular to the cell row 2 to form a grid-like power line. However, although the above-mentioned problems are solved, the power supply line 6 and the ground line 7 that cross the wiring area 4 impose regular restrictions on the wiring track, and as a result, the degree of freedom in wiring is significantly hindered. Furthermore, the arrangement of the logic cells 1 is also restricted, which brings about a new problem in that the efficiency of using general-purpose cells and wiring tracks is significantly reduced.

The present invention has been made in consideration of these circumstances, and its purpose is to stabilize the power supply line and reduce voltage drop without interfering with the arrangement of logic function cells and the degree of freedom in signal wiring. It is an object of the present invention to provide a highly practical semiconductor integrated circuit which is designed to reduce the amount of noise and prevent circuit malfunctions and latch-up phenomena.

The outline of the present invention is to provide an active element area in which a logic function cell is formed and a wiring area in which wiring lines are set and signal wiring is performed, and a power supply line and a ground line are provided penetrating the active element area and each In a semiconductor integrated circuit designed to supply power to logic function cells, auxiliary wires connected to the above power supply line and ground line are placed in empty areas of the wiring area where signal wiring is freely done according to the circuit specifications. By forming this structure, the power supply line is stabilized, thereby effectively achieving the above-mentioned purpose.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 schematically shows the planar configuration of the embodiment circuit, and the same parts in the conventional example shown in FIGS. 1 and 2 are denoted by the same reference numerals.

A plurality of general-purpose logic function cells 1 are formed on the semiconductor pellet 8 in accordance with predetermined arrangement regulations, each of which is composed of active elements such as transistors and passive elements such as resistors and capacitors. These logic function cells 1 are arranged in a predetermined number in the vertical direction to form a cell row block, and this block forming area is used as one active element area 3 and are provided in parallel at a plurality of locations at predetermined intervals. ing. The area between and around each active element area 3 is defined as a wiring area 4 for signal wiring. Therefore, the above-mentioned regions 3 and 4 are formed around the semiconductor pellet 8.
A bus line 9 consisting of a power line and a ground line is wired surrounding the cell line, and both ends of the bus line 9 are connected to the bus line 9, and a power line 6 and a ground line 7 are respectively arranged extending through the active element region 3 in the cell column direction. be done. Each logic function cell 1 is supplied with power through the power supply line 6 and ground line 7, and exhibits a predetermined logic function in response to a signal.

In the wiring area 4, signal wiring 5 for transmitting and receiving signals between the logic function cells 1 is freely wired along wiring tracks according to desired circuit function specifications. By forming the signal wiring 5, the connection of the cells 1 exhibiting the desired logical function is completed.

Thereafter, the auxiliary wire 10 is arranged using the empty area on the wiring area 4 where the signal wiring 5 has not been formed. This auxiliary line 10 is appropriately connected to the power supply line and the ground line 7 that pass through the active element region 3, and realizes a bypass route for the current path, and functions as an auxiliary power supply line or a ground line. . And this auxiliary line 10 is
As long as there is room in the wiring area 4, the wiring is provided in a mesh pattern using that empty area.

In the circuit of this embodiment configured in this manner, the auxiliary line 10 functioning as an auxiliary power supply line or a ground line is provided using a vacant area after the signal wiring 5 is arranged and formed. Therefore, the degree of freedom in the arrangement and wiring of the logic function cell 1 is not hindered. Further, since the auxiliary line 10 bypasses or disperses the current flowing through the power supply line 6 and the ground line 7, it substantially lowers the direct current resistance of the power supply line wiring and at the same time reduces its wiring inductance. Therefore, the causes of malfunctions and latch-up phenomena caused by voltage drops and spike voltages are effectively eliminated, and a logic function that can be expected to operate stably and with high reliability can be realized. Further, since the auxiliary line 10 is formed using a free area, it has the advantage of being highly versatile for various logical functions.

Note that the present invention is not limited to the above embodiments. In the embodiment, a connected cell type master slice type is explained, but it may be a single cell type, or a building block type or similar type can be applied as well. . Further, the number of auxiliary wires 10 and the locations where they are connected to the power supply wire 6, the ground wire 7, or the bus bar 9 may be determined according to the circuit function specifications. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams showing a conventional example, and FIG. 3 is a block diagram showing an embodiment of the present invention. 1...Logic function cell, 2...Cell column, 3...Active element area, 4...Wiring area, 5...Signal wiring,
6...Power line, 7...Grounding line, 8...Semiconductor chip, 9...Bus bar, 10...Auxiliary line.

Claims (1)

[Scope of Claims] 1. A plurality of element regions in which a plurality of active elements for realizing various logical functions are formed in a row, and a wiring track for interconnecting input and output terminals of the active elements. A wiring area is formed between each element area, and a power supply line and a ground line for supplying power to each of the active elements are respectively arranged and formed on the element area to realize a specified logical function. In a semiconductor integrated circuit in which signal wiring is arranged and formed on a wiring track in the wiring region, the element is arranged in a region where no signal wiring interconnecting the active elements on the wiring region is arranged and formed. 1. A semiconductor integrated circuit comprising auxiliary wires each connected to a power supply line and a ground line on a region.