JPS58164242A - Master slice type integrated circuit - Google Patents

Abstract

PURPOSE:To increase the margin against a noise by additionally forming at least two wirings of the same voltage as wirings of pectinated shape which supply power source voltage to cells forming an IC, thereby averaging the voltage distribution of an entire chip. CONSTITUTION:Many cells 2 are formed in a master slice type IC, power wirings 1 from a power source pad 3 are formed in a pectinated shape while containing current source cells 4 forming the cells 2, and contacted with the respective cells. In this structure, many power source wirings 6 to become 2-layer metals are further formed parallel to electrode wirings 1, power wirings 5 to become 1-layer metal at least not less than two are formed while perpendicularly crossing them, and the wirings 6 and 5 are connected via a through hole 7. In this manner, the wirings 5 and 6 which are equal to the voltage of the wirings 1 and cover the wirings 1 are formed in addition to the wirings 1, thereby alleviating the voltage shift of the power source voltage and increasing the margin against a noise of the cell isolated from the pad 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master slice type integrated circuit, and particularly to the routing of power supply wiring on a chip.

Conventionally, when the power supply pad tV of a master slice type integrated circuit is connected to only one side of the chip, the power supply layout is cross-grained as shown in FIG. In FIG. 1, reference numeral 1 indicates a power supply wiring, which is arranged in rows and columns on the chip and supplies power to nine circuit units (hereinafter referred to as cells) 2. 3 is a power pad. Fig. 2 shows a calculation of the potential shift of the power supply voltage due to the wiring resistance, assuming that the cell 4 with the diagonal legs is drawing out (or drawing in) current. In Figure 2, the potential shift of the power supply voltage is shown in Figure 1.
Since it is symmetrical with respect to the source pad 3, only the left half is shown. As seen in FIG. 2, the power supply voltage shift is uneven depending on the arrangement of cells on the chip. This potential shift is a factor that reduces the noise margin of the cell, which differs from the power supply voltage. Conventional wiring structure o#! In order to avoid this gap, improvements were made such as widening the wiring width to reduce wiring resistance9 and increasing the thickness of the wiring metal, but this increased the chip area and lowered the yield. There were some difficulties in manufacturing.

The present invention provides a master slice type integrated circuit which eliminates the above-mentioned drawbacks by simply making improvements in wiring, and which has a large margin against noise.

That is, one master slice integrated circuit according to the present invention.

In addition to the comb-like wiring that supplies power to each cell, at least two wirings having the same potential as the wiring are provided to average the potential distribution over the entire chip.

Embodiments of the present invention will be described below with reference to one drawing.

FIG. 3 is a diagram showing an embodiment of the layout of a master slice integrated circuit according to the present invention. Reference numeral 5 denotes a power supply wiring made of one layer of metal, and numeral 6 denotes a power supply wiring made of two layers of metal, which are connected by a through hole 7. The difference between Figure 3 and Figure 1 is that even if there are many current paths, the current distribution spreads over the entire chip, which alleviates the bias in the potential shift of the power supply voltage and also reduces the heat distribution. will also yield useful results.

Figure @4 shows the electric fII111 due to wiring resistance when assuming the same cell arrangement as in Figure *@1 and using the wiring structure shown in Figure 3.
It is a figure showing the calculation result of the electric potential shift of pressure. As shown in FIG. 4, the potential 77 of the power supply voltage is more relaxed in magnitude and bias than in FIG. -Comparing the maximum value of the potential shift of the power supply voltage, the potential shift of Fi in Figure 4 is 40% less than that of Figure @2 in one calculation.

In the third example, only one single-layer metal wiring is used on the horizontal axis, but it is clear that increasing the number of single-layer metal wiring on the horizontal axis is more effective in mitigating the potential shift of the power supply voltage. be.

Also, assuming a chip with 10 X11 cells in the calculation (21stW, 1lIJailZ), 9 is
As the number of cells increases, there is a greater possibility that the potential shift will increase, and the present invention is an effective means for alleviating this potential shift.

In addition, in Figure 3, the cross-grained wiring that supplies power to each cell and the newly installed wiring are placed in the binding no and are connected by a through hole. Even if -mK is provided, it is effective in alleviating the potential drift of the power supply voltage.

As can be seen from the above description, in the master slice integrated circuit according to the present invention, in addition to the comb-shaped wiring that supplies power to each cell, there are By making the above-mentioned improvements in the pattern design, the potential shift of the *S voltage can be alleviated without causing a single point on the right, and it can be changed from aS P and D to This has the effect of increasing the noise margin.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a conventional power supply wiring pattern and an example of the configuration of a master slice type integrated circuit, Fig. 2 is a diagram showing the potential shift of the power supply voltage due to the wiring 1w grinding pile in the configuration of Fig. 81! The figure is a diagram showing a power supply wiring pattern showing an embodiment of the present invention, and Figure @4 is a diagram showing a potential shift of the power supply voltage due to wiring resistance in the configuration of FIG. 3. In the diagram, l...Power distribution a, 2.°°°
...Cell arrangement, 3...Power pad, 4...
...Cell acting as a current source, 5...
1 layer metal interconnect % 6...2 layer metal interconnect 41.
7...Through hole connecting 1st and 2nd layer metal,
shows. Atsushi l Izukao...5 prefectures 8 Atsushi 3 mouths

Claims (2)

[Claims] (1) In a master slice type integrated circuit in which a plurality of circuit units having an arbitrary (b) circuit function are provided on a kl chip and a desired logical function is achieved by electrically connecting the circuit units. , a master slice type integration characterized in that each circuit unit is provided with power supply wiring laid in a comb pattern, and at least two wirings having the same potential as the wiring are provided in a direction perpendicular to the wiring. circuit. (2) The master slice type integrated circuit according to claim (1), characterized in that two interconnections orthogonal to each other are provided in different layers.