JPS6349957A - Common bus control system - Google Patents

Abstract

PURPOSE:To suppress the increment of execution time for data transfer by separating a control board detected at its abnormality from other control boards on the receiving side at the time of its detection and switching current data transfer to 1 to 1 type data transfer to continue the data transfer. CONSTITUTION:If a control board 1 receives an error signal from a control board 2 when the board 1 executes 1 to 2 type data transfer through a common bus 15, a control information changing means 10 is actuated and an address of the control board 2 transmitting the error signal out of addresses specified by the control information is erased. Afterthere, the control board 1 executes 1 to 1 type data transfer to a control board 3. After the end of the data transfer, data transfer from the control board 3 side to the control board 2 side is executed, so that the operating time of the control board 1 having a channel interface function can be reduced.

Description

[Detailed Description of the Invention] [Summary] In a magnetic disk control device that performs one-to-two data transfer between multiple control boards connected on a common bus, an abnormality occurs in one of the control boards on the receiving side. When an abnormality is detected, the control board in which the abnormality has been detected is disconnected, and data transfer is continued by switching to one-to-one data transfer, so as not to increase the execution time of data transfer.

[Industrial application field]

The present invention relates to a common bus control system in a magnetic disk control device that performs one-to-two data transfer between a plurality of control boards connected on a common bus.

[Conventional technology]

A magnetic disk control device is a device that performs input/output control of a magnetic disk device. It is connected to the channel section of a data processing device, and receives data from the main storage device via the channel section and transfers it to the magnetic disk device. The data is transferred to the main memory device via the channel section.

As is well known, in a magnetic disk drive, writing and reading cannot be performed until the disk is in a predetermined position.

A so-called access time is required, and in the worst case, it is necessary to wait for the time required for the disk to rotate once. For this reason, the use of cache memory has been considered in order to eliminate the most recent access time.

FIG. 4 is a diagram showing an example of a common bus control method in a conventional magnetic disk control device.

In the figure, 1 to 3 are control boards, 1a is a register provided in the control board 1, 14 is a cache memory, and 15 is a register provided in the control board 1.
is a common bus, 16 is a control line, 17 and 18 are signal lines, respectively.
31 is a magnetic disk control device, 32 is a channel section of a data processing device, and 37 is a magnetic disk device. The same symbols represent the same objects throughout all the figures below.

As shown in FIG. 4, the magnetic disk control device 31 in this case includes a control board 1 having a channel ink face function with the channel unit 32, a control board 2 having an ink face function with the magnetic disk device 37, and a cache memory. A control board 3 having an ink face function with 14 is connected to a common bus 15, and data is transferred in a one-to-two format from the control board 1 to the control boards 2 and 3 via the common bus 5. I do.

When the control board 1 starts data transfer between the control board 2 and the control board 3, the control board 2 transfers data to the disk device 37.
Writing to the disk device 37 is not performed until the disk comes to a predetermined position.Writing starts only when the disk comes to a predetermined position, but the control board 3 immediately caches the transferred data. The data is stored in the memory 14.

Therefore, the next time data is read from the magnetic disk device 37, since the data is stored on the cache memory 14, the data can be read from the cache memory 14 without reading data from the magnetic disk device 37.

By performing one-to-two data transfer and writing data on the cache memory 14 in this way, when the next time data is read from the magnetic disk device 37, if the target data is on the cache memory 14, the conventional Access time can be eliminated.

In the conventional one-to-two format data transfer, the magnetic disk drive 3
When writing/reading to/from control board 7, first control board 1
outputs control information on the control line 16 of the common bus 15. That is,
The control board 1 has a register 1a inside it, and one to two registers.
To transfer data in this format, set the address of control board 1 in the OX section of register 1a, the address of control board 2 in section Y of register 1a, and the address of control board 3 in section 2 of register 1a. The control board 2 and control board 3 connected to the control line 16 receive this control information and enter a reception mode.

When the control board for transmission and reception is determined in this way, the control board 1 outputs a sending signal to the signal line 17 and signal line 18 of the common bus 15 to send out data.

The control board 2 receives data via the common bus 15;
When received, a confirmation signal is sent back via the signal line 17, and when it cannot be received, an error signal is sent back.

The control board 3 also receives data via the common bus 15;
When received, a confirmation signal is sent back via the signal line 18, and when it cannot be received, an error signal is sent back.

Repeat these steps to transfer data.

[Problem that the invention seeks to solve]

However, in the conventional method, when data is transferred using the above procedure, if an error signal is issued from any control board, the data transfer is stopped and the data transfer is restarted from the beginning, so the time required for data transfer is reduced. The drawback was that it could double in the worst case.

[Means for solving problems]

The above problem is caused by the fact that, as shown in the principle diagram of FIG. A control board 1 that outputs and transmits control information specifying the address of the board 1 and the receiving control board 2.3.
The control board 2.3 outputs a transmission signal to the signal line 17.18 of the common bus 15, and the receiving control board 2.3 outputs a confirmation signal or an error signal to the signal line 17.18. In a system that performs transfer, when the transmitting control board 1 receives an error signal from any of the receiving control boards 2 and 3, it transmits the error signal from among the addresses specified in the control information. control board 2.3
This problem can be solved by adding control information changing means 10 for erasing the address.

[Effect]

According to the invention, the control board 1
When the control board 1 receives an error signal from the control board 2 during data transfer using the two-way method, the control information changing means 10 operates to change the error signal from among the addresses specified by the control information. Since the transmitted address of control board 2 is erased, control board 1 will be replaced by control board 3 from now on.
Data transfer is performed on a one-to-one basis.

After the completion, data is transferred from the control board 3 side to the control board 2 side, thereby reducing the operating time of the control board 1 having the channel ink face function.

〔Example〕

FIG. 2 is a diagram showing one embodiment of a common bus control method according to the present invention.

FIG. 3 is a time chart.

In the figure, IA is a control unit, 1b is a transmitting/receiving unit, and 1d is an IC.
is an AND gate, 1e is an OR gate, 1f and 1g are reset circuits, and 10-digit control information changing means.

Also in the common bus control system according to the present invention, the control board 1 issues control information to the control line 16 of the common bus 15.

That is, when performing data transfer in one-to-two format, register 1a
The address of the control board 1 is set in the OX section, the address of the control board 2 is set in the Y section of the register 1a, and the address of the control board 3 is set in the 2nd section of the register 1a, and the contents of the register 1a are sent to the control line 16.

The control board 2 and control board 3 connected to the control line 16 receive this control information and enter a reception mode. When the control board for transmission and reception is determined in this way, the control board 1 outputs a sending signal to the signal line 17 and signal line 18 of the common bus 15 to send out data.

The control board 2 receives data via the common bus 15;
Once received, a confirmation signal is sent back via the signal line 17. The control board 3 also receives data via the common bus 15 and returns a confirmation signal via the signal line 18 upon reception. Repeat these steps to transfer data.

The above is the same as the conventional system, but if the control board 2 returns an error signal via the signal line 17, the control board 1 changes the control information changing means 10 provided inside the control board 1.
The address of the control board 2 is deleted from the control information.

The present invention will be described in detail below with reference to the drawings.

The signal exchange circuit using the signal line 17 and signal line 18 has the configuration shown in FIG. The transmitter/receiver IC is connected to the signal line 18 and sends and receives transmission signals, confirmation signals, and error signals between the control board 3.

When the transmitter/receiver 1b receives the confirmation signal from the control board 2, it outputs a signal to the AND gate ld, and similarly the transmitter/receiver 1b
When c receives a confirmation signal from the control board 3, it outputs a signal to the AND gate ld.

Therefore, when a confirmation signal is sent from the control board 2 and the control board 3, an output is generated in the computer game 1-1d, and the control unit IA is driven to continue data transfer.

The control information changing means 10 according to the present invention includes an OR gate 1e,
A transmitter/receiver unit 1b consisting of reset circuits lf and 1g.
When an error signal is sent from the control board 2, it drives the reset circuit 1r, resets and erases the register 1aOY section, and outputs a signal to the OR gate 1e.

Further, when the transmitter/receiver IC receives an error signal from the control board 3, it drives the reset circuit 1g, and when the error signal is sent, it resets and erases the register 1aOZ section and outputs a signal to the OR gate 1e.

Therefore, if an error signal is sent from the control board 2, the Y part of the register 1a is reset, the address of the control board 2 is erased, the output is output from the OR gate e, and the control board 1, which controls the entire control board 1, is output. Publication IA mu the data transfer.

In this way, the control information changing means 10 changes the control information stored in the register la, and starts sending out the next data. For this reason, only the control board 3 continues to receive data from now on, and the control board 2 cannot receive data.

When this one-to-one data transfer is completed, since the correct data is stored in the cache memory 14, the cache memory 14 is transferred from the cache memory 14 through the control board 3, common bus 15, and control board 2 to the magnetic disk device 37. By writing data to the magnetic disk device 37, data can be transferred to the magnetic disk device 37 without using the control board 1 having the channel ink face function.

Figure 3 is a time chart that supplements the above explanation, and ■
■ is the timing when control information is output, ■ is the timing when data is transferred, ■ is the timing when the transmission signal is output, ■ is the timing of the confirmation signal issued by the control board 2,
2 represents the timing of the confirmation signal issued by the control board 3, 2 represents the timing of the error signal issued by the control board 2, and 2 represents the timing of the error signal issued by the control board 3.

In response to the transmission signal a of ■, the control board 2 sends the confirmation signal a of ■
, the control board 3 returns the confirmation signal a' of (3).

In response to the sending signal of ■, the control board 2 sends the confirmation signal of ■b°
, the control board 3 returns the confirmation signal b'' of ■.

However, in response to the transmission signal C in ■, the control board 2 returns the confirmation signal C' in ■, but the control board 3 does not receive a confirmation signal as shown in ■, and instead returns the error signal C'' in ■. For this reason, in response to the transmission signal d of ■, the control board 2 returns the confirmation signal d° of ■, but since no data is transferred to the control board 3, no confirmation signal or error signal is issued thereafter.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect of reducing the usage time of a control board having a channel ink face function.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 shows an example of a common bus control method according to the present invention. FIG. 4 shows an example of a common bus control method in a conventional magnetic disk control device. In the figure, 1 to n are control boards, IA is a control section, 1a is a register provided in the control board 1, 1b and IC are transmitting/receiving sections, 1d is an AND gate, 1e is an OR gate,
if and Ig are reset circuits, 10 is a control information changing means, 14 is a cache memory, 15 is a common bus, 16
are control lines, 17 and 18 are signal lines, 31 is a magnetic disk control device, 32 is a channel section of a data processing device, 3
7 is a magnetic disk device. ■ ■ Timekeya-1~Ban3 Figure

Claims (1)

[Claims] A plurality of control boards (1 to n) each have a common bus (15).
The control board (1) that sends data specifies the addresses of the control board (1) that sends data and the control boards (2, 3) that receive data on the control line (16) of the common bus (15). The transmitting control board (1) outputs the control information to be transmitted, and the receiving control board (2, 3) transmits the transmission signal to the signal line (17, 18) of the common bus (15). In a system that performs one-to-two data transfer via the common bus (15) by outputting a confirmation signal or an error signal to the transmitting control board (1), the receiving control board (1) outputs a confirmation signal or an error signal to When the error signal is received from any of the control boards (2, 3), the control board (2, 3) that sent the error signal from among the addresses specified in the control information
) A common bus control system characterized in that a control information changing means (10) for erasing the address of the bus is added.