JPS6349944A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To reduce debugging operation at the time of abnormal interruption processing by successively updating an interruption request circuit in specific addresses assigned in a program memory in accordance with interruption requests. CONSTITUTION:A general register array 1 temporarily stores an arithmetic state and data processed by an arithmetic logic computing element 2. An interruption control circuit 10 calculates a vector table address in accordance with an interruption request inputted from an external apparatus and transfers the calculated address value to a memory control circuit 5. A counter increment circuit 11 to be also used as an interruption request frequency writing means successively counts up respective interruption request inputted to the circuit 10, and while successively updating the number of interruption requests, writes the counted value in a specific address assigned in the program memory 4 through a data bus 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic processing device that analyzes various instruction data and executes a program.

[Conventional technology]

Conventionally, this type of arithmetic processing equipment, that is, the central processing unit (
CPU), interrupt processing (IRQ processing) is executed as follows.

First, the program uses iRQ to perform an interrupt (iRQ).
Initialize the Q vector table. The iRQ vector table is usually provided in the memory space of the central processing unit (CPU), and can be read/written from the CPU.
ite) is possible, and the start address of the program corresponding to each interrupt is written in the iRQ vector table. Furthermore, which software interrupt uses a vector in the vector table is generally fixed in terms of hardware within the CPU.

For example, as shown in Figure 4, the vector of interrupt factor A is "0".
'' number, the interrupt factor B vector is set to address ``4'', and the addresses of each interrupt factor A and B are written to address ``0'' or ``4'' to make the CPU capable of iRQ.

When interrupt factor B occurs in this state, the CPU saves the current program counter and various registers, and sets the contents of address "4" as the new program counter. Therefore, when the processing program for interrupt factor B is executed and the command at the end of processing (in this example, the i RET instruction) is executed, the CPU restores the previously saved program counter and various registers.

In a CPU that executes such operations, the order in which interrupts occur may be assumed. For example, a program is created with the assumption that interrupts will occur in the order of interrupt factor B and interrupt factor A, but in reality, this may occur in the opposite order, or a completely unexpected state such as an interrupt may occur. If this occurs, the program will behave abnormally.

[Problem that the invention seeks to solve]

In the past, it was extremely difficult to investigate the causes mentioned above under such conditions, and it was necessary to use a dedicated analysis device different from the CPU or provide a trace means to analyze the condition within the program. , there were problems such as the inability to investigate the cause.

This invention was made to solve the above problems, and by understanding the frequency of occurrence of interrupt requests for each interrupt cause, it is possible to debug when one interrupt processing execution becomes abnormal. The purpose is to obtain arithmetic processing that can reduce operations.

[Means for solving problems]

The arithmetic processing device according to the present invention, when each interrupt request occurs,
The interrupt request number writing means is provided for sequentially updating and writing each interrupt request number to a specific address allocated in the program memory for each interrupt request.

[Effect]

In this invention, for example, when each interrupt request is generated from each external device, the interrupt request number writing means writes the number of interrupt requests to a specific address allocated in the program memory in response to each interrupt request. We will update each one sequentially.

〔Example〕

FIG. 1 is a block diagram for explaining the configuration of an arithmetic processing device showing an embodiment of the present invention, in which 1 is a general-purpose register array, and an arithmetic logic unit (ALTJ) 2 processes arithmetic states and data. Hold temporarily. 3 is a data bus, 4 is a program memory, and reading is controlled based on data written to each address of the memory control circuit 5.

6 is a program counter that sequentially instructs the next instruction to be executed; 7 is an instruction register that holds the instruction code sent and received via the data bus 3;

An instruction decoder 8 analyzes the instruction code held in the instruction register 7 and transfers the analyzed instruction to the control circuit 9. Reference numeral 10 denotes an interrupt control circuit that calculates a vector table address in response to an interrupt request input from an external device, and transfers the calculated address value to the memory control circuit 5. Reference numeral 11 denotes a counter incrementing circuit constituting the interrupt request number writing means of the present invention, which sequentially inputs each interrupt request inputted to the interrupt control circuit 10, and when the next interrupt request occurs, the respective address "
Read the contents of “4” and “12” and add “1” to the contents.
is added, and the count value is written to address "4" or address "12" in the same manner as described above.

FIG. 2 is a schematic diagram for explaining the memory space of the program memory 4 shown in FIG. This corresponds to the interrupt request A input to the circuit 10. A first counter area 22 is set, for example, at address "4" of the program memory 4, and stores the count value counted by the counter incrementing circuit 11 when the interrupt request A is input. Note that the initial value is that all 4 bytes are "0". 23 is, for example, "
The second vector area is set at address 8'' and corresponds to the interrupt request B input to the interrupt control circuit 1o. A second counter area 24 is set, for example, at address "12" of the program memory 4, and stores the count value counted by the counter increment circuit 11 when the interrupt request B is input. Note that the initial value is that all 4 bytes are "0".

Next, the interrupt request management control operation according to the present invention will be explained with reference to FIG.

FIG. 3 is a flowchart for explaining the interrupt request management control operation according to the present invention. In addition, (1) to (14
) indicates each step.

While executing the program stored in the program memory 4 shown in FIG. 1, the control circuit 9 waits for an interrupt request A or B to be input to a port (not shown) of the interrupt control circuit 10. 1) When interrupt request A or interrupt request B occurs, the interrupt control circuit 1o notifies the control circuit 9 of the interrupt input (2). Next, the control circuit 9 transfers the program counter 6 and the general-purpose register array to the program memory 4.
(3) 0 Next, the interrupt control circuit 10 calculates the address of the interrupt vector corresponding to the input interrupt request A or interrupt request B (4), and stores the calculated address in the counter increment circuit 11. (5).

The counter increment circuit 11 generates an address obtained by adding "4" to the given address, that is, the first counter area 22
6), read the contents of that address 7), add rlJ to that value 8), and write the added count value to the first counter area 22 (9).
. Next, the interrupt control circuit 10 waits for a write end notification (10), and when the write end notification occurs, the interrupt control circuit 10 waits for a write end notification (10). The address "4" or address "12" shown in FIG. 2) is notified to the control circuit 9 (11). Next, the control circuit 9 reads the content written to address "4" or address "12" (12) and writes it to the program counter 6 (13).
), and program execution control continues (14). Here, the program is interrupted or stopped at any timing, and the first counter area 22, second counter area 24
Read the contents of. That is, the first counter area 22
．． The frequency of occurrence of each interrupt request can be determined from the contents of the second counter area 24.

In the above embodiment, the case where the counter increment circuit 11 initializes the first counter area 22 and the second counter area 24 at an arbitrary timing has been described, but it is also possible to initialize the first counter area 22 and the second counter area 24 at an arbitrary timing. good. Further, in the above embodiment, the first counter area 22. Although the case where the reading of the contents of the second counter area 24 is executed at an arbitrary timing has been described, it may be controlled to be executed at the start or end of each interrupt request.

〔Effect of the invention〕

As explained above, this invention, when each interrupt request occurs,
We have provided an interrupt request count writing means that sequentially updates and writes each interrupt request count to a specific address allocated in the program memory for each interrupt request, so the frequency of occurrence of each interrupt request can be accurately traced. This has the excellent advantage of greatly improving debugging efficiency when a program executes abnormally.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the configuration of an arithmetic processing device showing one embodiment of the present invention, FIG. 2 is a schematic diagram for explaining the memory space of the program memory shown in FIG. 1, and FIG. The figure is a flowchart for explaining the interrupt request management control operation according to the present invention, and FIG. 4 is a schematic diagram for explaining the conventional interrupt processing operation. In the figure, 1 is a general-purpose register array, 2 is an arithmetic logic unit,
3 is a data bus, 4 is a program memory, 5 is a memory control circuit, 6 is a program counter, 7 is an instruction register,
8 is an instruction decoder, 9 is a control circuit, 10 is an interrupt control circuit, and 11 is a counter increment circuit. Figure 1 Figure 2 Figure 4 Address ↓ 3rd

Claims (1)

[Claims] In an arithmetic processing unit that interrupts a running program in response to multiple interrupt requests input from an external device and executes a specific interrupt processing routine based on a vector value written to a specific address in a program memory, The present invention is characterized by comprising an interrupt request count writing means for sequentially updating and writing each interrupt request count to a specific address allocated in the program memory for each interrupt request when each interrupt request occurs. Arithmetic processing unit.