JPS6349238B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a driving method for driving a display, and particularly to a display driving circuit that obtains a display driving signal.

There has been remarkable technological progress in electronic desk calculators in recent years, especially in the complementary circuit configuration of insulated gate field effect transistors (hereinafter abbreviated as CMOS).
One notable example is the technology of reducing power consumption by combining a large-scale integrated circuit (hereinafter referred to as LSI) and a liquid crystal display. Various methods of driving liquid crystal displays have been studied, but in the case of computers with a large number of characters to display, a dynamic drive method that divides display segments in time and sequentially applies display signals has been proposed. As is well known, it has been adopted.

In the case of a liquid crystal display, the response time is much slower than that of a light emitting diode, etc., so the time division of the dynamic drive is set to about 1/2 to 1/4 to increase the duty cycle of the display period. An example of a drive circuit using a 1/3 duty cycle, which is currently widely used, will be explained with reference to FIG. Decoder 1
A, B, C, D, E,
F, G, and DP are decoded outputs corresponding to each segment of the display body. Each segment 1a, 1b, 1c, 1d, 1e of the character shape of the liquid crystal display 2,
1f, 1g, and 1dp are displayed by applying a voltage between opposing electrodes provided on their front and back surfaces. The back electrodes of segments 1f, 1a, and 1b are commonly connected to electrode _h11 as shown by dotted lines, and similarly, the back electrodes of segments 1e, 1g, and 1c are connected to electrode _h12 , and the back electrodes of segments 1d and 1dp are connected to electrode h12. They are commonly connected to h ₁₃ as shown by the dotted lines. Furthermore, the surface electrodes of segments 1f and 1e are connected to electrode S ₁₁ , and similarly the surface electrodes of segments 1f and 1e are connected to electrode S 11.
g, 1d surface electrode is electrode S ₁₂ , segment 1
The surface electrodes b, 1c, 1dp are connected to electrode _S13 . The inverting circuit 3 is a circuit for alternating the polarity of the voltage applied to each segment of the liquid crystal display 2 at a constant cycle for AC driving. Flip-flops F ₁₁ , F ₁₂ and F ₁₃ are for storing display information to be supplied to electrodes S ₁₁ , S ₁₂ and S ₁₃ . In the circuit shown in FIG. 1, in order to display a necessary character shape on the liquid crystal display 2, a selection signal is sequentially applied to each common electrode h ₁₁ , h ₁₂ , h ₁₃ , and each segment is displayed at a duty cycle of 1/3. The output of decoder 1 is each electrode h ₁₁ ,
The electrodes are selected by decoder output switching signals h′ ₁₁ , h _{′ 12 ,} h′ 13 synchronized with the respective selection signals h ₁₂ , h ₁₃ .
When h ₁₁ is selected, the outputs F, A, and B of the decoder 1 corresponding to segments 1f, 1a, and 1b are selected by switch circuits T _F , T _A , and T _B that are turned on by the switching signals, respectively, and the flip-flops F ₁₁ ,F ₁₂ ,
Stored in F ₁₃ . Similarly, when electrode _h12 is selected, decode outputs E, G, and C corresponding to segments 1e, 1g, and 1c are output from flip-flops _F11 to _F13, respectively.
Furthermore, when _h13 is selected, decode outputs D and DP corresponding to segments 1d and 1dp are stored in the flip-flops, respectively. flipflop F ₁₁ ,
The outputs of F ₁₂ and F ₁₃ are converted by the inverting circuit 3 into drive signals whose polarities are periodically inverted, and then the outputs of the liquid crystal electrodes S ₁₁ ,
Supplied to S ₁₂ and S ₁₃ . In Figure 1, for simplicity, only the display of one digit is explained, but depending on the number of digits of characters to be displayed, three flip-flops are provided for each digit, and the display data corresponding to each digit is sequentially decoded. 1, and the decoded output of each digit is sequentially stored in the flip-flop corresponding to each digit. In this case, the driving circuit is relatively simple because three flip-flops are required for each digit, but it is necessary to constantly supply data of each digit to the decoder 1. Since data of each digit is continuously supplied to the decoder 1, the arithmetic processing circuit continues to operate at all times. In CMOS, where data movement accounts for most of the power consumption, constantly supplying data to the decoder is a major obstacle to reducing power consumption.

For this reason, recent technology uses random access memory (hereinafter referred to as RAM) as a storage circuit for arithmetic processing circuits to minimize data movement during the display period after arithmetic processing, and the arithmetic processing circuits are mostly in operation during display. Display drive circuits that have extremely low power consumption without any interference are already in use. Second
The figure shows an example of such a drive circuit. The decoder 11 converts a signal input into a segment drive signal, and has the same function as the decoder 1 shown in FIG. The liquid crystal display 12 includes segments 2a to 2g, 2dp, the back electrodes of segments 2f, 2a, 2b are commonly connected to electrode _h21 , and the back electrodes of segments 2e, 2g, 2c are connected to electrode _h22 . connected in common, segment 2d,
A 2dp back electrode is commonly connected to electrode _h23 . Electrode S ₂₁ has surface electrodes of segments 2f and 5e, S ₂₂ has surface electrodes of segments 2a, 2g, and 2c, and S ₂₃ has segments 2b, 2c, and 2dp.
surface electrodes are connected to each other. Inversion circuit 13
is for reversing the polarity of the drive signal for driving the display body 2 in an alternating current manner, and the switching circuit 17
The flip-flop is activated by selection signals h _{' 21} , h' ₂₂ , and h' ₂₃ that are synchronized with the drive signals h ₂₁ , h ₂₂ , and h ₂₃ , respectively.
It has a function to switch the output of F _f , F _e , F _a , F _g , F _d , F _b , F _c , F _dp , and multiple switch circuits T _A to _{T G} , T _dp
It is made up of. In this circuit, a signal is converted into each segment signal by a decoder 11, and all of the converted signals are temporarily stored in a flip-flop. The flip-flop F _f stores the display signal of the segment 2f, and the flip-flop F _e stores the display signal of the segment 2e and the flip-flop F _a
segment 2a, flip-flop F _g has segment 2g, flip-flop F _b has segment 2b, flip-flop F _b has segment 2b, flip-flop F _c has segment 2.
Display signals of segment 2dp are stored in c and flip-flop _Fdp , respectively. In this way, once all display signals are stored in the flip-flop, the selection signals h' ₂₁ , h _{' 22} , h' ₂₃ synchronized with the drive signals h ₂₁ , h ₂₂ , h ₂₃ of the back electrodes are used to select the signals necessary for display. The output of the flip-flop corresponding to the segment is selected, and the inverting circuit 13 drives the electrodes S ₂₁ , S ₂₂ , and S ₂₃ while periodically inverting the polarity. In this method, all display data is stored in the flip-flop in advance, so once the display signal of each digit is input to the decoder 11, there is no need to continue supplying the signal to the decoder. Because of this, the arithmetic processing circuit does not need to operate continuously during display, and circuits that use static RAM, which does not require a clock to retain data, as the arithmetic storage circuit have ultra-low power consumption of only a few microwatts during display. display drive circuits have become possible. However, as is clear from Fig. 2, eight flip-flops are required for each digit in the case of the display shown in Fig. 2 to store each segment signal. 65 or more
Requires 70 flip-flops. Furthermore, since such a large number of flip-flops must be specially provided separately from the calculation memory used in normal calculation processing, there is a drawback that a large area is required for this purpose. Furthermore, these many flip-flop circuits require individual input signals and clock pulses for read control, so even if they are constructed using the latest integrated circuit technology, it is inevitable that the scale will be very large. In the past, in order to store all segment information and display it with low power, a large amount of sacrifice had to be made.

SUMMARY OF THE INVENTION An object of the present invention is to provide a drive circuit that overcomes these obstacles of conventional circuits, has low power consumption, and is miniaturized.

A display drive circuit according to the present invention stores a display drive signal in a memory circuit for storing arithmetic processing signals,
The present invention is characterized in that a periodic display drive signal is obtained from this memory circuit by addressing this memory circuit in synchronization with the cycle of driving the display. Here, in the present invention, preferably, during the display drive period, a portion of the memory circuit for storing the arithmetic processing signal that stores the display drive signal is used separately from the remaining portion. In addition, in this memory circuit, display information corresponding to display body segments driven for display in the same drive period is stored in the same address, and display information corresponding to the same drive digit of the display body is stored in the same digit. It is preferable.

The present invention provides a display driving circuit provided in an information processing device including an arithmetic memory and an arithmetic processing circuit.
A first data line for reading, a first address line for supplying an arithmetic address to the arithmetic memory, and for separating the arithmetic memory into a first memory section and a second memory section. a switch means provided, a means for writing a display drive signal into the first memory section, and a means for reading out the display drive signal written in the first memory section in synchronization with a display cycle. a second address line for applying a display address to the first memory section; and a second data line for supplying the read display drive signal to the display; a period in which the calculation memory is separated into the first memory section and the second memory section;
A display drive signal written in the first memory section according to the display address given from the second address line is periodically read out via the second data line. It is.

Next, one embodiment of the present invention will be described with reference to FIG.

The arithmetic processing circuit 30 controls a predetermined arithmetic unit of the information processing device including the display drive circuit. This arithmetic processing circuit 30 is connected to a read/write control circuit (hereinafter referred to as R/W circuit) 33 via a connection line A to control it. R/
The W circuit 33 is connected to the memory circuits 31 and 32 by connection lines 33-1, 33-2, . . . 33-n. Memory circuits 31 and 32 are both RAM
They are connected to each other by a switch circuit 36 so that they can be considered as a substantially integrated unit. Addressing of memory circuits 31 and 32 is performed by address circuit 34. Here, the memory circuit 32 includes an address circuit 34.
Address lines 34-1, 34-2, 34-3 from
is applied via the switching circuit 35. The address line 34 of the address circuit 34 is connected to the memory circuit 31.
-4,...34-n are directly applied. The switching circuit 35 connects the address line 34 to the memory circuit 32.
-1 to 34-3 are connected during arithmetic processing, and the display synchronizing signals h' ₃₁ , h' ₃₂ , and h' ₃₃ are connected when not arithmetic processing is performed. , the control signal D is inverted by the inverter 35-7, and is applied to the AND gates 35-1, 35-3, and 35-5 to which the display synchronization signals h' ₃₁ , h' ₃₂ , and h' ₃₃ are respectively input. The other control signal D is applied to the address lines 34-1,
AND with 34-2 and 34-3 input respectively
It is applied to gates 35-2, 35-4, and 35-6. The output of AND gates 35-1 and 35-2 is 2
Row 32 of memory circuit 32 via input OR gate
-1. AND gate 35-3 and 35
The output of -4 is connected to row 32-2 of memory circuit 32 via a two-input OR gate 35-9. Similarly, the outputs of AND gates 35-5 and 35-6 are each connected to row 32-3 of memory circuit 32 via a two-input OR gate 35-10. Outputs S ₄₁ , S ₄₂ , and S ₄₃ of the memory circuit 32 are connected to the surface electrodes of each segment of the liquid crystal display 22 via an inversion circuit 23 that inverts the display drive signal at a constant cycle. Each surface electrode of the segments 3f and 3e receives the drive output S ₃₁ from the inverting circuit 23 corresponding to the output S _41.
Similarly, segments 3a, 3g,
Each surface electrode of 3d has a drive output corresponding to the output S ₄₂
Connected to _S32 . Segments 3b, 3c,
Each 3dp surface electrode is similarly connected to the drive output S ₃₃ corresponding to the output S ₄₂ . On the other hand, the back electrodes of segments 3f, 3a, and 3b are commonly connected to electrode _h31 , the back electrodes of segments 3e, 3g, and 3c are commonly connected to electrode _h32 , and the back electrodes of segments 3d and 3dp are connected to electrode h31. ₃₃ are commonly connected. Each of these electrodes h ₃₁ , h ₃₂ , h ₃₃ is supplied from a selection signal generation circuit 39, and this selection signal generation circuit 39 sequentially supplies a selection signal to each of these electrodes h ₃₁ , h ₃₂ , h ₃₃ . Although the above description has been made with respect to a single digit display, it goes without saying that other digit display bodies may be similarly arranged in parallel to this display. During the calculation processing period, the transistor of the switch circuit 36 is turned on when the control signal D takes a high level.
The RAM 32 is equivalent to the RAM 31 and its writing and reading operations are controlled by the R/W circuit 33. At this time, the address of the RAM 32 is specified by the control signal D input to the switching circuit 35 from the address lines 34-1 to 34 from the address circuit 34.
-3 is given. Calculation processing in a computer has a large number of storage circuits to temporarily store intermediate data at the processing stage depending on the content to be processed, but the data that must be finally stored at the end of the calculation is very limited. In many cases, it is only a portion of the data. For example, a desktop calculator that processes trigonometric functions or exponential-logarithmic functions may temporarily store four to five types of numerical values in order to obtain a solution, and requires a storage capacity commensurate with this. However, in these processes, more than half of the RAM is often on standby without storing data while the calculation results are being displayed after the calculation is completed. After performing arithmetic processing in RAM31 and 32, the data to be finally stored is stored in RAM.
The display information converted into the segment signal is stored using the storage circuit 32 left over from the memory stored in 31.
Cells f ₁ , a ₁ , b ₁ , e ₁ , g ₁ , c ₁ , N, in the RAM 32
d ₁ and dp ₁ are the segments 3f and 3f of the liquid crystal display 22, respectively.
The display contents correspond to 3a, 3b, 3e, 3g, 3c, 3d, and 3dp, respectively, and cell N does not have a corresponding segment in this embodiment, so even if it stores arbitrary data, it will not affect the display. does not cause To write data converted into segment display information to the RAM 32, the display information is input from the RAM to the decoder circuit 101 via the R/W circuit 33, converted to segment display information, and this segment display information is sent to the arithmetic processing circuit 30. The data may be written into the RAM 32 by the R/W circuit 33 under the control of the R/W circuit 33. As another method, since the R/W circuit 33 and the arithmetic processing circuit 30 are connected to the RAM 32, the segment display can be converted to a read-only storage circuit (hereinafter abbreviated as ROM), which is a part of the arithmetic processing circuit 30. Easy to program by programming the contents
It is possible to write data converted into segment information into the RAM 32. According to this method, there is no need to provide a special decoding circuit. During the arithmetic processing period, signals corresponding to the processing contents are output to the outputs S ₄₁ , S ₄₂ , and S ₄₃ of the RAM 32, but during the arithmetic processing period, the display is generally turned off as is done on desktop calculators, so they are common. The electrode selection circuit 39 is prohibited from selection by a control signal D so as not to output a selection signal to any electrode. During the display period, the common electrode selection circuit 39 sequentially supplies selection signals to the electrodes h ₃₁ , h ₃₂ , and h ₃₃ by switching the control signal D (in this case, switching to a low level), and the writing and reading of the RAM 32 are common. When the switch circuit 36 is turned off, the line is separated and the RAM 32 is connected to the RAM 31 and R/
It operates completely independently from the W circuit 33. At this time, display synchronization signals h' ₃₁ , h' ₃₂ , and h' ₃₃ are applied by the switching circuit 35 to address the RAM 32 at the same time. When the selection signal is applied to the electrode _h31 of the display body 22, the display synchronization signal _h'31
Address 32-1 of RAM32 is specified and RAM
32 outputs S ₄₁ , S ₄₂ , S ₄₃ have cells f ₁ , a ₁ , b _{1 ,} respectively.
After the content is output and converted into an AC signal by the polarity inversion circuit 23, the segments 3f, 3a,
Display 3b. Similarly, when the selection signal is applied to the electrode _h32 , the address 32-
2 is designated by the display synchronization signal h' ₃₂ , and cells e ₁ , g ₁ , c ₁ corresponding to segments 3e, 3g, 3c
signals are generated at outputs S ₄₁ , S ₄₂ , S ₄₃ . electrode
When h ₃₃ is selected, the address 32-3 is similarly specified by the display synchronization signal h' ₃₃ , and _{the cell d 1 ,}
The memory contents of the cell dp ₁ are outputted to _S43 , and the arbitrarily written N is outputted to the output _S41 . However, the output _S41 during the _h33 selection period is not displayed on the electrode because there is no corresponding segment. In this way, during display, the contents of RAM 32 are displayed in synchronization h' ₃₁ , h' ₃₂ ,
It is periodically read out and displayed by h' ₃₃ . Since the RAM 31 can be operated independently of the display even during the display period, arithmetic processing can be performed within the storage capacity of the RAM 31 if necessary.
Figure 4 shows the RAM used in the embodiment shown in Figure 3.
The configuration of the circuits 31 and 32 and the configuration of the switch circuit 36 for separating the RAM write and read common lines,
RAM cells 132-1, 132-2 belong to the memory circuit 32, and RAM cells 131-1, 131-2
belongs to RAM31. The configuration of each of these RAM cells is the same, and will be explained below based on RAM cell 132-1. 20, 21 are N conductivity type field effect transistors (hereinafter abbreviated as NMOS) 40, 41
is a P-conductivity field-effect transistor (PMOS)
CMOS
The power supply V _D on the NMOS side, which forms a memory circuit by interconnecting the inverter circuits in the configuration, is a negative voltage,
O _V is applied to the power supply V _S on the PMOS side.
NMOS 44 and 45 are for address selection and are selected by address input line 50. The write and read common lines 48 and 49 of the RAM cells have a phase relationship that is opposite to each other in terms of logic levels. NMOS4
6, 47 are switches T ₁ , T ₂ . . . provided to separate the write and read common lines 48, 49 in the middle.
... corresponds to T _o and is turned off by control signal D to separate the two RAMs 31 and 32. Fourth
The basic RAM cell shown in the figure is a circuit with very low power consumption because no current flows between the power supplies V _D and V _S during data storage. In the embodiments shown in FIGS. 3 and 4, the display contents of the RAM are read out at very long cycles of several hundred Hz during the display period, and only the portion of data required for display changes. This not only makes it possible to realize a device with very low power consumption due to low power consumption due to changes in data, but also to create a dedicated This has the great effect of greatly reducing the chip area when integrated into an integrated circuit, since a part of the calculation memory can be used for display content storage without providing a flip-flop group. In addition, since segment information can be written directly from the arithmetic processing circuit to the RAM cells, complex glyph compositions can also be performed using the ROM of the arithmetic processing circuit.
Versatility due to the fact that it can be processed by a program is also a great advantage.

Although the present invention has been described above based on Examples, the present invention is not limited to such Examples.
The display body is not limited to a liquid crystal display body, and the configuration of the RAM circuit etc. can be arbitrarily configured.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a conventional display drive circuit.
FIG. 2 is a block diagram showing another conventional display drive circuit. FIG. 3 is a block diagram showing a display drive circuit according to an embodiment of the present invention. FIG. 4 is a block diagram showing another conventional display drive circuit.
FIG. 3 is a circuit diagram showing the configuration of a RAM section. 2, 12, 22...Liquid crystal display, 3, 13, 2
3... Inversion circuit, 7, 17... Switch circuit,
1, 11...decoder circuit, 1a-1d, 2a-
2d, 3a to 3d, 3dp, 2dp, 1dp... display segment, F ₁₁ , F ₁₂ , F ₁₃ , F _a to _{F d1} , F _dp ...
Flip-flop, 31, 32...RAM, 33
...R/W circuit, 30... Arithmetic processing circuit, 34...
...Address circuit, 35...Switch circuit, 39...
...Selection signal generation circuit.

Claims (1)

[Claims] 1. In a display drive circuit provided in an information processing device including an arithmetic memory and an arithmetic processing circuit, a first data line for writing/reading data to/from the arithmetic memory, and an arithmetic address assigned to the arithmetic memory. a first address line for supplying a display drive signal to the first memory section; a switch means provided for separating the arithmetic memory into a first memory section and a second memory section; and a second address line for applying a display address to the first memory section for reading out the display drive signal written in the first memory section in synchronization with a display cycle. and a second supplying the read display body drive signal to the display body.
data line, and during a period when the arithmetic memory is separated into the first memory section and the second memory section by the switch means, the data line applied from the second address line A display drive circuit, characterized in that a display drive signal written in the first memory section according to a display address is periodically read out via the second data line.