JP2708947B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for realizing a display operation on a display means such as a liquid crystal display device.

2. Description of the Related Art For example, in a simple matrix type liquid crystal display device, a plurality of transparent strip electrodes which are orthogonal to each other are formed on a pair of transparent substrates, and a matrix-like address is set in a display area to realize display. At this time, the scanning of the column direction electrodes of the liquid crystal display device is performed along the row direction by the row direction driving means,
Display data is output for each column direction electrode. On the other hand, the row direction electrodes are scanned in the column direction by the column direction drive circuit. When writing display data to a liquid crystal display element using such a configuration, in order to prevent a situation in which a DC voltage is applied to the liquid crystal, a writing voltage based on the display data is:
Alternating is performed so that the polarity is periodically inverted by a control signal called a polarity inversion signal. In other words, write voltages of mutually opposite polarities are periodically applied to the liquid crystal.

FIG. 6 is a block diagram showing an electrical configuration of a typical conventional liquid crystal display device 101. As shown in FIG. The liquid crystal display device 101 includes a liquid crystal display element 102 driven by a matrix and a liquid crystal display element 1.
02, a column direction drive circuit 103 for performing the column direction scan, and a row direction drive circuit 104 for performing the row direction scan and outputting display data. The display data from the display data output unit 105 provided in the row direction drive circuit 104 is converted by the level shifter 106 from the transistor level to the liquid crystal display element 1.
The voltage level is converted to the drive level of 02, and its inverted output and non-inverted output are connected to a pair of NAND circuits 107 and 108 and a pair of NOR circuits 109 and 110, respectively.

Note that the polarity inversion signal FRM for externally performing the above-described display voltage AC conversion process is input to the row direction drive circuit 104 from the outside, and the polarity inversion signal FRM ′ whose voltage level has been increased by the level shifter 111 is output to each of the NAND circuits 107 and 108. And NOR circuit 109,1
Enter individually in 10. On the other hand, in the row direction drive circuit 104,
Four different drive potentials V1 to V4 applied to the liquid crystal display element 102 are generated. Each of the potentials V1 to V4 includes switching circuits 112 and 113 formed of P-channel MOS (metal oxide semiconductor) transistors. Switching circuits 114 and 115 composed of N-channel MOS transistors are individually connected. Outputs of the switching circuits 112 to 115 are connected to a common line 116 and input to the liquid crystal display element 102.

In the row direction driving circuit 104 having such a configuration, each of the switching circuits 112 to 115 has four types of states, that is, a high level and a low level of the data waveform from the level shifter 106, and a high level and a low level of the polarity inversion signal FRM '. Circuits 107 and 108 and NOR circuit 10 based on a combination of
According to the outputs of 9,110, one of the combinations is turned on for each combination, and at this time, the remaining three are controlled to be cut off.

In this conventional example, at the timing when the polarity of the polarity inversion signal FRM switches between a high level and a low level, P
Based on the difference in responsiveness between the channel switching circuits 112 and 113 and the N channel switching circuits 114 and 115, that is, based on the characteristic that the P channel switching circuits 112 and 113 respond more slowly than the N channel switching circuits 114 and 115, each of the switching circuits 112 to 115 At the same time, a conduction period occurs. As a result, the drive potentials V1 to V4 are simultaneously connected to the common line 116, and a through current flows through the common line 116. Thereby, the row direction drive circuit 104
However, there is a problem that the power consumption of the device increases and the through current may damage the circuit.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned technical problems, to prevent the generation of a through current in a liquid crystal display device, and to provide a data processing device with low power consumption.

Means for Solving the Problems The present invention provides (a) a method in which a plurality of row direction electrodes and a plurality of column direction electrodes are respectively formed on opposing surfaces of a pair of transparent substrates, and a liquid crystal is provided between the transparent substrates. (B) key input operation means 3, 4, 10; (c) battery 25; (d) power supply circuit 26 connected to battery 25 to generate various reference voltages (E) a liquid crystal power supply circuit 16 that changes the liquid crystal power supply potential in response to a contrast signal and switches between an operation state and a stop state in response to a control signal; and (f) the processing circuit 12, which includes a power supply 25, 26, the control signal is generated and supplied to the liquid crystal power supply circuit 16, the address data AD for the liquid crystal display device 11 and the display data corresponding to the address data AD are supplied, and the density data is set. (G) the common drive circuit 1 The clock signal generating circuit 23, 24 for generating a clock signal
And a common signal control circuit 27 that uses the clock signals from the clock signal generation circuits 23 and 24 to apply a common signal to the row direction electrodes to scan and drive the common electrode, and a clock signal from the clock signal generation circuits 23 and 24 A memory control circuit for selectively transferring to the segment drive circuit 17 in accordance with the address data AD from the processing circuit 12
A contrast control means for deriving a contrast signal in response to the density data from the processing circuit and providing the contrast signal to the liquid crystal power supply circuit, and controlling the contrast of the liquid crystal display device by the liquid crystal power supply potential from the liquid crystal power supply circuit 46,171 and a polarity inversion signal FR that is periodically inverted and converted to AC
And (h) a plurality of segment drive circuits 17, each of which drives a column-direction electrode of the liquid crystal display device 11 in correspondence with address data. Each segment drive circuit 17 is further provided with a polarity inversion signal FR to display a plurality of potentials different from each other.
A display voltage output unit 61 for generating V1 to V4, and potential selection means 69 to 72 connected to a plurality of different potentials V1 to V4, respectively, and each output connected in common and connected to each column direction electrode. Selection control means 64 to 67 for making any one of the plurality of potential selection means 69 to 72 conductive based on the display data and the polarity inversion signal; and predetermined in each time the polarity of the polarity inversion signal is switched. A segment driving circuit 17 including a switching forcing unit 74 for limiting all potential selecting units 69 to 72 to a cutoff state during a period.

According to the present invention, the data processing device is provided with the key input operation means 3, 4, and 10, so that data can be freely input. Further, since the liquid crystal power supply circuit 16 is provided, the liquid crystal power supply potential can be changed in response to the contrast signal, and the operation state / stop state can be switched in response to the control signal. Also, since the processing circuit 12 is provided,
The address data AD and display data corresponding to the address data AD can be supplied to the liquid crystal display device 11.

The data processing device is provided with a common drive circuit 1, and the common drive circuit 1 includes a clock signal generation circuit.
Since 23, 24, the common signal control circuit 27, the memory control circuit 22, and the contrast control means 46, 171 are provided,
A common signal can be applied to the row direction electrodes by using a clock signal to scan and drive the row electrodes, and the address data AD from the processing circuit 12 can be selectively transferred to the segment drive circuit 17. Further, the contrast of the liquid crystal display device 11 can be controlled in response to the density data from the processing circuit 12. Further, since the common drive circuit 1 is provided with the control circuit 19, the polarity inversion signal FR, which is periodically inverted and converted into AC, is supplied to the segment drive circuit.
17 can be output. As described above, since the data processing device has various functions, data processing can be performed efficiently.

Further, the data processing device is provided with a segment drive circuit 17, and the segment drive circuit 17 is provided with potential selection means connected to each column direction electrode, and is connected to a plurality of mutually different potentials. The selection control means makes any one of the plurality of potential selection means 69 to 72 conductive based on the display data and the polarity inversion signal FR input at a predetermined cycle. At this time, a plurality of potential selecting means
If there is a difference in response between 69 and 72, the polarity inversion signal FR
In the present invention, in order to solve this problem, a switching forcing means 74 is provided, which is predetermined every time the polarity of the polarity inversion signal FR is switched. During the period, all the potential selection means 69 to 72 are regulated to be in the cutoff state.

This makes it possible to prevent a situation in which all the potential selection means 69 to 72 are conductive, a plurality of potentials are connected to the row direction electrodes, a through current flows, and an increase in power consumption of the segment driving circuit 17 can be prevented. It is possible to prevent a failure of the electric circuit due to the current.

Embodiment FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2 using a common drive circuit 1, and FIG. FIG. The data processing device 2 has a so-called notebook size, and the first operation unit 3 and the second operation unit 4 are configured to be freely opened and closed by a coupling unit 5. The second operation unit 4 includes a cursor key 6, a function setting key 7, a character input key 8, a numeric key 9, and the like. On the other hand, on the first operation unit 3, a so-called transparent touch key 10 and a liquid crystal display device 11 are arranged.

Such a data processing device 2 includes, for example, a CPU (central processing circuit) 12 including a microprocessor or the like.
The CPU 12 has the transparent touch key 10 and the second
A RAM (random access memory) 13 to which each key input means of the operation unit 4 is connected and which is used as a storage area for various input data and a working area for data during operation, and a CPU
ROM that stores programs that regulate 12 control operations, display font data, calendar data, etc.
(Read only memory) 14 is connected.

Further, the CPU 12 has a timing circuit 15 for timing, a common drive circuit 1 for controlling the display operation of the liquid crystal display device 11 as described later, and a common drive circuit 1 based on a contrast signal from the common drive circuit 1. The liquid crystal power supply circuit 16 is connected to a liquid crystal power supply circuit 16 that changes the operating state / stop state according to a control signal from the CPU 12. The common drive circuit 1 has a plurality (8 in this embodiment).
), And controls the display state of the liquid crystal display device 11 together with the common drive circuit 1. The liquid crystal display device 11 is configured such that a common electrode 11c and a segment electrode 11d are formed on opposing surfaces of a pair of transparent substrates 11a and 11b, and a liquid crystal layer 11e is interposed therebetween.

A block diagram of the common drive circuit 1 is shown in FIG. The common drive circuit 1 is supplied with a write / read control signal R / W, a clock signal φ, a busy signal BY, a chip enable signal CE, and the like from the CPU 12, and is supplied with address data AD, display data DI, and the like. 19 is provided. The display data DI is input through the buffer 20. Further, the common drive circuit 1 includes a polarity inversion signal FR which will be described later as a frame signal, a control signal DIS for controlling ON / OFF of display by segment electrodes, and a clock signal L.
And CK to the segment drive circuit 17. As described above, such a data processing device 2 is a notebook-sized portable device, and various reference voltages necessary for the operation of the data processing device 2 are generated from a power supply circuit 26 connected to a battery 25.

A data processing circuit 21 is connected to the control circuit 19 and the CPU 12
After performing a predetermined logical operation (such as SET, AND, OR, XOR, etc.) on the address data and display data transferred from the device, the data is transmitted to the segment drive circuit 17. The memory control circuit 22 determines to which of the segment driving circuits 17 the address data sent from the CPU 12 is to be transferred, and generates a relative address in any of the selected segment driving circuits 17. The timing generation circuit 23 generates a clock signal used for various arithmetic processing in the common drive circuit 1 and the like, and receives a reference clock signal from the oscillator 24.

The common signal control circuit 27 and the common-side decoder 28 use the clock signal generated by the timing generation circuit 23 to generate a common signal supplied to the common electrode of the liquid crystal display device 11. The control circuit 19 includes a window processing circuit 29.
Is connected, and the contrast adjustment circuit 46 is connected to the liquid crystal display device 11.
Is stored on the display, and the density data is set by the CPU 12. The contrast adjustment of the liquid crystal display device 11 is based on the density data in the contrast adjustment circuit 46,
This is performed by the liquid crystal power supply circuit 16 shown in FIG.
A liquid crystal voltage input section 171 is provided for taking the liquid crystal power supply potential from the LCD into the common drive circuit 1.

FIG. 4 shows a display voltage output section of the segment drive circuit 17.
FIG. 61 is a block diagram showing a configuration of a 61. Segment drive circuit
A display data generating unit 62 implemented by, for example, a RAM (random access memory) is provided in the display device 17. Display data to be output and display addresses of the display data in the liquid crystal display device 11 are supplied from the common drive circuit 1. . When writing display data to the liquid crystal display device 11, in order to prevent a situation in which a DC voltage is applied to the liquid crystal, the write voltage based on the display data is periodically set to a polarity by a control signal called a polarity inversion signal. Are inverted so that is inverted. In other words, write voltages of mutually opposite polarities are periodically applied to the liquid crystal.

Display data output section provided in segment drive circuit 17
The display data from 62 has a voltage level converted from, for example, a transistor level to a drive level of the liquid crystal display device 11 by a level shifter 63, and its inverted output and non-inverted output are
Each pair is connected to a pair of NAND circuits 64 and 65 and a NOR circuit 66 and 67, respectively.

The display voltage output unit 61 receives the polarity inversion signal FR from the control circuit 19 in the common drive circuit 1 for performing the above-described display voltage AC conversion process, and the polarity inversion signal whose voltage level has been increased by the level shifter 68. FR 'is individually input to each of the NAND circuits 64 and 65 and the NOR circuits 66 and 67.

On the other hand, the display voltage output unit 61 generates four different drive potentials V1 to V4 applied to the liquid crystal display device 11, and each potential V1 to V4 has a P-channel MOS (metal oxide semiconductor). Switching circuit consisting of transistors with structure
69, 70 and switching circuits 71, 72 each comprising an N-channel MOS transistor are individually connected, and the output of each switching circuit 69, 72 is connected to a common line 73 and input to the liquid crystal display device 11. You.

The polarity inversion signal FR ′ output from the level shifter 68 is input to the switching forcing circuit 74. The switching forcing circuit 74 includes a NAND circuit 75 and a NOR circuit 7 to which the polarity inversion signal FR 'is input.
The output of the NAND circuit 75 is input to the NAND circuits 64 and 65 via the inverting circuit 77, and is also input to the NOR circuit 76 via the pair of inverting circuits 78. On the other hand, N
The output of the OR circuit 76 is supplied to the NOR circuit 66,
The signals are input to the NAND circuit 75 via a pair of inverting circuits 80, respectively. Here, the capacitors C1 and C2 connected to the output stages of the inverting circuits 77 and 79 are gate capacitors, respectively.

In the display voltage output unit 61 having such a configuration, each of the switching circuits 69 to 72 includes a high level and a low level state of the data waveform from the level shifter 63 and a switching forcing circuit.
NAND circuits 64, 65 and NOR based on a combination of high and low levels of switching signals FNA, FNR to be described later from 74
According to the outputs of the circuits 66 and 67, one of the combinations is turned on for each combination, and the remaining three are controlled to be in the cutoff state.

FIG. 5 is a time chart for explaining the operation of this embodiment. The polarity inversion signal FR 'has the same phase as the polarity inversion signal FR, and is a signal whose level is increased. In this embodiment, a switching signal FNA input to the NAND circuits 64 and 65 and a switching signal FNR input to the NOR circuits 66 and 67 are generated from the polarity inversion signal FR 'using the switching forcing circuit 74.

Since the switching signal FNR is obtained by NOR operation between the polarity inversion signal FR 'and the switching signal FNA, the switching signal FNR is generated at the rising timing t1 of the polarity inversion FR' shown in FIG.
Also stand up. On the other hand, since the switching signal FNA is obtained by performing an AND operation between the polarity inversion signal FR ′ and the switching signal FNR, the switching signal FNA is affected by the gate capacitance C2, and the period T1 determined by the gate capacitance C2 from the rising timing t1. It rises at the separated time t2. Thereafter, the fall timing of the polarity inversion signal FR '
During a period T2 until t3, the switching signals FNA and FNR are both at a high level.

When the polarity inversion signal FR 'falls at the falling timing t3, the switching signal FNA becomes the polarity inversion signal FR' and the switching signal FNR.
, And falls immediately at the falling timing t3. At this time, since the switching signal FNR is obtained by performing a NOR operation between the polarity inversion signal FR 'and the switching signal FNA, the gate capacitance is obtained from the falling timing t3.
It falls at time t4 separated by a period T3 corresponding to C1. In a period T4 after the time t4, the switching signals FNA and FNR are both at a low level.

In this manner, the P-channel switching circuits 69, 7
A switching signal FNA that controls 0 and a switching signal FNR that controls N-channel switching circuits 71 and 72 are generated.

In response to the data in the non-inverted state output from the shift register 63 being “1” or “0”, the outputs NA1 and NA2 of the NAND circuits 64 and 65 and the outputs NR1 and NR of the NOR circuits 66 and 67
2 is as shown in Tables 1 and 2 below. The symbol Z in each table indicates a high impedance state.

In the period T2, when the display data is “1”, only the output NA1 is valid, and the driving potential V1 is selected. When the display data = "0", only the output NA2 is valid, and the drive potential V3 is selected. In the period T4, when the display data is "1", only the output NR2 is valid, and the driving potential V2 is selected. In the display data "0", only the output NR1 is valid, and the driving potential V4 is selected.

At this time, the polarity inversion timings t1 and t of the polarity inversion signal FR '
In periods T1 and T3 separating predetermined periods T1 and T3 from 3, all the switching circuits 69 to 72 are in the cutoff state, and the common line 73 is in the high impedance state. Accordingly, it is possible to prevent a situation in which a through current is generated at the time of switching the polarity inversion signal FR 'as described in the section of the related art, and to reduce the power consumption of the segment drive circuit 17. it can. Further, by preventing the through current, it is possible to prevent the occurrence of an electrical failure in the segment drive circuit 17 and the like.

Effect of the Invention As described above, according to the present invention, since the data processing device has various functions, data processing can be performed efficiently. In the segment drive circuit 17, when a difference occurs in the response of the plurality of potential selection units 69 to 72, all the potential selection units 69 to 72 may be turned on at the inversion timing of the polarity of the polarity inversion signal FR. It is conceivable that in the present invention, in order to solve this problem, the switching forcing means 74 is provided, and all the potential selecting means 69 to 72 are restricted to the cutoff state for a predetermined period every time the polarity of the polarity inversion signal FR is switched. Like that. Thereby, all the potential selection means 69 to 72 are turned on, a plurality of potentials V1 to V4 are connected to the row direction electrodes, a through current flows, and an increase in power consumption of the segment drive circuit 17 can be prevented. It is possible to prevent a failure of the electric circuit due to the through current.

[Brief description of the drawings]

FIG. 1 is a block diagram of a common drive circuit 1 according to an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2, FIG. 3 is a plan view of the data processing device 2, and FIG. FIG. 5 is a time chart for explaining the operation of the present embodiment, and FIG. 6 is a block diagram of a typical conventional liquid crystal display device 101. As shown in FIG. 1 ... common drive circuit, 2 ... data processing device, 11 ...
Liquid crystal display device, 17 Segment drive circuit, 61 Display power output unit, 69-72 Switching circuit, 73 Common line, 74 Switching adjustment circuit

Claims (1)

(57) [Claims] 1. A liquid crystal in which a plurality of row direction electrodes and a plurality of column direction electrodes are respectively formed on opposing surfaces of a pair of transparent substrates, and a liquid crystal layer is interposed between the transparent substrates. (B) key input operation means 3, 4, 10; (c) battery 25; (d) power supply circuit 26 connected to battery 25 to generate various reference voltages; A liquid crystal power supply circuit 16 that changes the liquid crystal power supply potential in response to a signal and switches between an operation state and a stop state in response to a control signal; and (f) a processing circuit 12, which receives power from power supplies 25 and 26. A processing circuit 12 for generating the control signal and supplying it to the liquid crystal power supply circuit 16, supplying address data AD for the liquid crystal display device 11 and display data corresponding to the address data AD, and setting density data; (G) The common drive circuit 1 generates a clock signal That clock signal generating circuit 23, 24
And a common signal control circuit 27 that uses the clock signals from the clock signal generation circuits 23 and 24 to apply a common signal to the row direction electrodes to scan and drive the common electrode, and a clock signal from the clock signal generation circuits 23 and 24 And a memory control circuit 22 for selectively transferring the data to the segment drive circuit 17 in response to the address data AD from the processing circuit 12.
And derives a contrast signal in response to the density data from the processing circuit 12 and supplies it to the liquid crystal power supply circuit 16.
A common drive circuit comprising: contrast control means 46 and 171 for controlling the contrast of the liquid crystal display device 11 by the liquid crystal power supply potential from 16; and a control circuit 19 for periodically inverting the polarity and outputting an alternating polarity inverted signal FR. (H) a plurality of segment drive circuits 17, each of which scans the column direction electrode of the liquid crystal display device 11 so as to display display data corresponding to the address data. Each segment drive circuit 17 is further provided with a polarity inversion signal FR, and a plurality of different potentials V1
To V4, and a plurality of potential selection means 69 to 72 connected to the plurality of potentials V1 to V4 different from each other, each output being connected in common and connected to each column direction electrode. Selection control means 64 to 67 for turning on any one of the plurality of potential selection means 69 to 72 based on the display data and the polarity inversion signal; and a predetermined period every time the polarity of the polarity inversion signal is switched. A segment driving circuit 17 including a switching forcing unit 74 for restricting all of the potential selecting units 69 to 72 to a cutoff state.