JPS60100193A - Display body driving system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a driving method for driving a display, and particularly relates to a display driving circuit that obtains a display driving signal.

In recent years, there have been remarkable technological advances in electronic desk calculators, especially large-scale integrated circuits (hereinafter referred to as LSI) based on complementary circuit configurations of insulated gate field effect transistors (hereinafter referred to as CMO8) and liquid crystal displays. A notable example of this is the technology for reducing matrices by combining the following. Various studies have been made regarding the driving method of the liquid crystal display, but in total! 4. t
M&'? ? It is well known that in cases where the number of digits of characters to be displayed is large, a dynamic drive system is adopted in which segments of the display body are time-divided and the display @ symbol is sequentially applied.

In the case of a liquid crystal display, the response time is 11 fJ, which is lower than that of a light emitting diode, etc. Because it is slow in G, the dynamics is reduced by setting the time division of Wb WB to about 172 to 174 to increase the duty cycle of the display period. circuit 1
An example will be explained with reference to FIG. The decoder 1 converts the output from the arithmetic circuit into a segment drive signal for the sound display body.A, 11. C, D, H, F.

G and Dr are decoded outputs corresponding to each segment of the display body. Each segment l of the character shape of the liquid crystal display 2
a, lb, IC, ld, le, If, Ig, and ldp are provided on their front surfaces and are displayed by applying a voltage between opposing electrodes. Segment If.

The six back electrodes la and lb are commonly connected to the electrode h□ as shown by the dotted line, and similarly the 4/4 of the segment l'le+1g+1'
1 Back side - 1 pole is electrode hlffi, 7gmen) ld, 1
The dpL0v surface electrodes are commonly connected to the electrode h0 as shown by dotted lines. 'Also segments 1f and 1e
The surface IL4A< is connected to the electrode 8IIVC31z, and the surface electrodes 1a, ig, and td are connected to the electrode 8IIVC31z, and the surface electrodes 1a, ig, and td are connected to the t pole st.
! In addition, the surface electrodes of segments lb, Ic, and ldp are 'delectable poles S1. It is connected to the. The inversion circuit 3 is the liquid crystal display 2
This is a circuit for alternating current driving by alternately switching the polarity of the voltage applied to each segment at regular intervals. Nori, flop F'i,, F□, F1° are t poles S11 r S11
* This is used to store display information supplied to S18. In the circuit shown in FIG. 2, in order to display a necessary character shape on the liquid crystal display 2, a selection signal is sequentially applied to each common 11C&h and eh11+h13, and each segment is displayed at 1/3 duty cycle. The output of the decoder 1 is for each electrode, □, h□, h1. The decoder output switching signal fi'll * h ? is synchronized with each selection signal of fi'll * h ? t T
When electrode h11 is selected by h'18, segment) If
, la.

Outputs F, A, and B of the decoder 1 corresponding to 1b are selected by switch circuits TF, TA, and TB that are turned on by a switching signal, respectively, and a flip-flop F□.

Fat, Fl K are stored. Similarly, when electrode h
In □, when h11 is selected, decode outputs corresponding to segments) 1d and 1dp and l)P are stored in 7 and 0, respectively. Pretending to be a gruff frog? , 1. p□.

The output of F is converted into a drive signal whose polarity is periodically reversed by the inverting circuit 3, and then the liquid crystal electrode S111 SII #
S1. supplied to In Figure 1, only the display for one digit is explained for the sake of simplicity, but depending on the number of digits of the displayed character, three 7-lip blocks are set for each digit to display the display according to each digit. Sequentially supply data to decoder 1,
The decode output of each digit is 7s, 0, which corresponds to each digit.
．． sequentially stored in the log.

In the case of this method, the circuit is relatively simple because only three digits are needed for each digit, but it is necessary to constantly supply data of each digit to the decoder 1. Since data of each digit is continuously supplied to the decoder 1, the arithmetic processing circuit continues to operate at all times. In OMO8, where data movement occupies most of the power consumption, φ, which always supplies data to the decoder, is a major obstacle to reducing power consumption.

For this reason, recent technology uses random access memory (hereinafter abbreviated as AM) as a storage circuit for arithmetic processing circuits to minimize the movement of data during the display period after arithmetic processing, and the arithmetic processing circuits are also used for most of the display period. Display drive circuits that do not operate and consume extremely low power consumption are also commonly used. ◇Figure 2 shows an example of such a drive circuit. It has the same function as the decoder 1 shown in FIG. 1. The liquid crystal display 12 has each segment 28~
2g, 2dp, segment) 2f.

2a, 2b Imen I! The poles are commonly connected to the electrode h□,
The back electrodes of segment 2ee2g+20 are commonly connected to electrode btt, and the Mlill of segment 2d12dp
The electrodes are commonly connected to electrode htl. electrode 811
8. The surface electrodes of segments 2f and 2e are provided. , are connected to the surface electrodes of segments) 2a, 2g, and 2C, and to Sl, are connected to the surface electrodes of segments) 2b, 2c, and 2dp, respectively.

The inverting circuit 13 inverts the polarity of the drive signal for driving the display body 2 in an alternating current manner, and the switching circuit 17 outputs a selection signal h'□+ synchronized with the drive signals of the electrodes h11 #hfl e hII, respectively. "911". Flip 70, Ff, Fe, Fa, Fg, Fd, Fb,
It has a function of switching the outputs of Fc and Fdp, and is composed of multiple switch circuits TA to TGeTdp. In this circuit, a signal is converted into each segment HQ signal by a decoder 11, and all of the converted signals are temporarily stored in Nori, Gufuro, and Pu. The display signal of the segment 2f is stored in the flip-flop Ff, and similarly, the display signal of the segment 2f is stored in the flip-flop Ff.
segment 2e1 flip-flop, and segment 211. Flip-flop Fg has segment 2
gm Segment 2b for flip 70 knob Fb, segment 2bs for 7 lip flop Fb, segment 2c for flip flop Fc.

The display signals of segment 2dp are stored in the flop Fdp. In this way, some clips 70
After storing all the display signals in the back-facing electrode, select all the outputs of the clip-flops corresponding to the segments necessary for display using the selection signal hsth' Then, the inverting circuit 13 periodically reverses the polarity of the electrode St@
+ 811 + Drive S-engine. In my method, all the display data is stored in the flip-flop, so the display signal of each phase is stored in the decoder 1 once.
1, there is no need to continue supplying signals to the decoder.For this reason, the ylL arithmetic processing circuit does not need to operate at all during display, making it possible to use static AM that does not require any clocks or clocks to hold data. In the circuit used as the arithmetic storage circuit, it has become possible to create a display drive circuit with ultra-low power consumption, with power consumption during display of only 1 μW. However, as is clear from Fig. 2, in the case of the display body shown in Fig. 2, there are 8 digits per digit and 8 digits and various codes for storing each segment signal. An electronic calculator that displays 65 to 70 flip-flops is required. Furthermore, these numerous flow, flow, and program circuits require individual input signals and clock pulses for read control, so even if they are constructed using the latest integrated circuit technology, it is inevitable that the scale will be extremely large. . In order to memorize all the segment information and display it with low power consumption, in the past, one had to be prepared for a great deal of sacrifice. A display driving method according to the present invention is characterized in that the display driving circuit obtains a periodic display driving signal. In the present invention, it is preferable that during the display drive period, the part of the memory circuit for storing the arithmetic processing signal that stores the display drive signal is used separately from the rest of the memory circuit. Also, in this memory circuit, during the same drive period It is preferable that the display information corresponding to the display segment to be driven for display be stored in the same address, and all the display information corresponding to the same drive digit of the display body be stored in the same digit.

Therefore, according to the present invention, a memory circuit that stores an arithmetic processing signal, a first address circuit that specifies an address of the memory circuit by an address control signal during an arithmetic processing period, and a display body are driven in synchronization with the cycle. It is equipped with a second address circuit that selects the address of the memory circuit, and a separation circuit that separates some or all of the input/output lines of the memory circuit in response to a control signal. By specifying all addresses, separating a part of the memory circuit by a separation circuit when driving the display, and specifying the address of the separated memory circuit by a second address circuit, periodic information can be obtained from the separated memory circuit. A display drive circuit that obtains a display drive signal is obtained.

Next, one embodiment of the present invention will be described with reference to FIG.

The arithmetic processing circuit 30 controls a predetermined arithmetic section of the information processing device including the display drive circuit. W circuit) 33 to control it. The R/W circuit 33 connects the memory circuits 31 and 32 with connection lines 33-1, 33-2.・・・・・・33-
connected by n.

Both memory circuits 31 and 32 are composed of RAM.

Addressing of the memory circuits 31 and 32, which are connected to each other by a switch circuit 36 so that they can be considered as substantially one unit, is performed by an address circuit 34. Here, the address #! from the address circuit 34 is sent to the memory circuit 32. 34-1, 34-2
, 34-3 are applied via the switching circuit 35. The address line 34- of the address circuit 34 is connected to the memory circuit 31.
4. ...34-n is directly applied. The switching circuit 35 is connected to the memory circuit 32 address 2-in 34-1~
34-3 is connected to the inverter 35-3 during arithmetic processing, and the control signal is connected to the inverter 35-3. 7, and display this as the display synchronization signal "31 + "Mlt"
AND gates 35-1 and 3 with 11 inputted respectively
5-3 and 35-5, and the other control < ps is applied to AND gates 35-2.35-4.35 to which addresses 2-in 34-1.34-2.34-3 are respectively input.
-6 is applied. The outputs of AND gates 35-1 and 35-2 are connected to row 3 of memory circuit 32 through two gates.
Connected to 2-1. AND) Gates 35-3 and 35-
The output of 4 is connected to row 32-2 of memory circuit 32 via two-way gate 35-9. At the same time, the outputs of AND gates 35-5 and 35-6 are t''L2 and 0
row 32- of the memory circuit 32 through 35-10
Connected to 3.

The output "41*"41+Su of the memory circuit 32 is connected to the surface electrode of each segment of the liquid crystal display 22 via an inversion circuit 23 that inverts the display drive signal at a constant cycle. Segment) Each surface electrode of 3f and 3e has an output of 8
Similarly, each surface electrode of the segments 3a, 3g, and 34 is connected to a drive output S corresponding to the output S. The surface electrodes of the segments 3b, 3c, and 3dp are similarly connected to a drive output 818 corresponding to the output S. On the other hand, the back electrodes of segment) 3f, 3a, and 3b are commonly connected to the electrode hst, and segment) 3e,
The back electrodes of 3g and 3C are commonly connected to the electrode h, and the back electrodes of segment 3d and 3dP are connected as electrodes.

are commonly connected. Each of these electrodes hII e
Company h yh is given from the selection signal generation circuit 39, and this selection signal generation circuit 39 generates each of these electrodes hIll +
A selection signal is sequentially supplied to hll+83m. In addition,
In the above explanation, the display body for one digit has been described, but it goes without saying that the display bodies for other digits are arranged in a similar manner so that they are arranged in parallel with this display body. During this period, the transistor of the switch circuit 36 turns ON and both signals take a high level.

The FIRAM 32 is equivalent to the AM 31, and its writing and reading operations are controlled by the R/W circuit 33. At this time, addresses 2-in 34-1 to 34-3 from the address circuit 34 are assigned to the RAM 3z by a control signal input to the switching circuit 35. Arithmetic processing in a computer has a large number of storage circuits to temporarily store intermediate data at the processing stage depending on the content to be processed, but the data that must be finally stored at the end of the calculation is very limited. In many cases, it is only a portion of the data. For example, a desktop that processes trigonometric functions and exponential-logarithmic functions! 'I calculators require a platform to temporarily store the numbers in categories 4 to 5a in order to store the solutions, and a storage capacity commensurate with that is required. However, in these processes, more than half of the RAM is often on standby without storing data while the calculation result is being displayed after the calculation is completed. After performing arithmetic processing using RAM 31.32, the data to be finally stored is 1
(The display information converted into segment signals is stored using the storage circuit 32 that is left over from the AIV 131.RA
Cell f1*”1sbl+’1gl*’1mN in M32
5'ldl's are the segments 3f of the liquid crystal display 22, respectively.
, 3m, 3b, 3e, 3g, 3c.

The display content corresponds to 3d and 3dp, and there is no corresponding segment in this embodiment of Cell N Hiro.
Even if arbitrary data is stored, the display will not be affected. To write data converted into segment display information into the RAM 32, the display information is input from the AM to the decoder circuit 101 via the R/W circuit 33, converted into segment display information, and this segment display information is sent to the arithmetic processing circuit. AM3 by the R/W circuit 33 under the control of 30
It is good to write 2 to 0. Alternatively, 几AM32
Since the 几/W circuit 33 and the arithmetic processing circuit 30 are connected to the , the conversion contents of the segment display must be programmed into the read-only memory circuit (hereinafter abbreviated as R, OM) which is the arithmetic processing circuit 3001 section. It is possible to easily write data converted into segment information to R and AM32. According to this method, there is no need to provide a special decoding circuit during the 0 operation processing period)? , output S4 of AM32
1 p S41 + S48 output a signal according to the processing content, but during the arithmetic processing period, the common electrode selection circuit 39 is used to turn off the display as is generally done on desktop calculators.
During the display period, selection is prohibited by a control signal so that no selection signal is sent to any electrode.

In addition to switching the control signal (in this case switching to a low level), the common electrode selection circuit 39 selects the electrode h81 r h! a+h
A selection signal is sequentially supplied to the AM32, and the write and read common lines of the AM32 are separated by turning off the switch circuit 36, and the AM32 is connected to the AM31 and the R/W circuit 3.
It operates completely independently from 3. At this time, RAM
32 is specified by the switching circuit 35 using the display synchronization signal "U*"B□h'3. is given. Display body 2
When the selection signal is given to the second electrode h□, the address 32-1 of the AM32 is specified by the display synchronization signal "it", and the output of the AM32 is S41 e Sa + S.
The contents of cells f, , a, , and b are output to u, and after being converted into AC signals by the polarity inversion circuit 23, they are displayed on the segments 3f, 3a, and 3b1 of the crystal 18.

When a colleague is given a selection signal to electrode hn, 几A
The address 32-2 of M32 is specified by the display synchronization signal hSt, and the segments) ae, 3g, and acvc correspond to the outputs S41 r
SU#S4! occurs in Display synchronization is done in the same way when electrode has is selected (address 32-3 is specified by No. 11r, output S, cell d1.S, cell d
The h memory contents of p, are output, and the arbitrarily written N is output to the output 841. However, the output S41 of the selected period is not displayed because there is no corresponding segment. .

In this way, while displaying, the contents of 几AM32 are displayed synchronized.
The readout and display output is performed periodically by the ``II m''h'ss. Since the RAM 31 can be operated independently of the display even during the display period, the RAM 31 can be used if necessary.
It is possible to perform arithmetic processing within the storage capacity of . Figure 4 shows the RAM circuit 31 used in the example shown in Figure 3.
．． 32 and the configuration of the RAM write/read common line separation switch circuit 36, 几AM cell 132-1.
, 132-2 are included in the memory circuit 32, and the AM cell 13
1-1.131-2 is stored in the RAM31.The configuration of each of these RAM cells is the same, and hereinafter referred to as RAM cell 13.
This will be explained based on 2-1t. 20.21 is an N4 wide field effect transistor (hereinafter abbreviated as NMO8), 40.41 is a P-conductor 1JL type is combined with a negative effect transistor (hereinafter abbreviated as pMos) 42.43, and the inverter circuit of CMO8 configuration is connected. The power supply VD on the NMO'8 side, which forms a memory circuit by connection, is a negative voltage, PMOS1
Ov is applied to it and vs of 111. N.M.O.
844 and 45 are for address selection and address input h
The write and read common lines 48 and 49 of the 0 AM cell selected by M50 must have a mutually opposite phase relationship in terms of logic levels. oNMO846°47 is common for write and read [48, 49'x separated at the middle This corresponds to the switches T, fil, ...+11n, which are provided to
．． 32e Separate 0 1 (as shown in Fig. 4) Since no current flows between the data storage medium VD and 78 in the basic AM cell, the circuit consumes very little power. In the embodiment shown in Figure 4, several hundred fl during the display period.
The display contents of AM are read out in a very long cycle of z, and only the part of the data required for display changes.
For this reason, not only can a device with very low power consumption due to small dissipation force caused by changes in data be realized, but also
Dedicated 7s, 70s for memorizing the displayed contents. This has the great effect of significantly reducing the on-chip product when integrated circuits because it does not require a chip. Further, since the segment information can be directly convoluted into the hole AM cell from all the arithmetic processing circuits, it is also possible to process complex character shape synthesis using the ROM program of the arithmetic processing circuit, which has a great advantage of versatility.

Although the present invention has been described above based on examples, the present invention is not limited to such examples, and the display body is not limited to liquid crystal displays, and the configuration of the RAM circuit etc. may be arbitrary. It can be done.

[Brief explanation of drawings]

Is Figure 1 a conventional display drive circuit? FIG. 2 is a block diagram showing another conventional display drive circuit, and FIG. 3 is a block diagram showing a display drive circuit according to an embodiment of the present invention.
FIG. 4 is a circuit diagram showing the configuration of the RAM section of the embodiment of FIG. 3. 2.12.22...Liquid crystal display, 3,13,2
3...Inversion circuit, 7.17...Switch circuit, 1゜11--Decoder circuit, 1 a to ld
, 2a-2d, 3a-3d, 3dp,
2dp, 1dl)...Display segment%
k 11 *F, , F18. F a~Fd,
, F dp-kawa・-7 lipfrog, 31, 32
・・・-・I is also AM, 33-・-・-kL/W circuit, 3
゜... Arithmetic processing circuit, 34... Address circuit, 35... Suitsuna tooth path, 39...
...Selection signal generation circuit. Agent Patent Attorney Uchihara, Susumu 1h/Figure

Claims (1)

[Claims] A plurality of first electrodes, a plurality of second electrodes provided corresponding to each of the plurality of first electrodes, and means for applying a synchronization signal to sequentially energize the plurality of first electrodes. a display unit which displays using a first electrode energized in synchronization with the synchronization signal and a second electrode corresponding to the first electrode; a calculation memory circuit; means for sequentially addressing different rows of the memory circuit in synchronization with the energization of the respective first electrodes during the display period of the memory circuit, and the second electrode is driven by the output of the memory circuit. Display body pivoting method 0 characterized by l