JPS6348254U - - Google Patents
Info
- Publication number
- JPS6348254U JPS6348254U JP13875986U JP13875986U JPS6348254U JP S6348254 U JPS6348254 U JP S6348254U JP 13875986 U JP13875986 U JP 13875986U JP 13875986 U JP13875986 U JP 13875986U JP S6348254 U JPS6348254 U JP S6348254U
- Authority
- JP
- Japan
- Prior art keywords
- data
- error detection
- detection line
- bus
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
- Bus Control (AREA)
Description
第１図は本考案装置の一例を示す構成概念図、
第２図は第１図における応答回路の構成ブロツク
図である。
ＳＹ１〜ＳＹｉ……通信装置、ＢＳ……外部バ
ス、Ｂ１……アドレス・データバス、Ｂ２……制
御バス、Ｂ３……エラー検出線、ＢＳＥ……内部
バス、ＩＣ１……比較回路、ＲＰＳ……応答回路
。
FIG. 1 is a conceptual diagram showing an example of the device of the present invention;
FIG. 2 is a block diagram of the response circuit shown in FIG. 1. SY1 to SYi ...Communication device, BS...External bus, B1 ...Address/data bus, B2 ...Control bus, B3 ...Error detection line, BSE...Internal bus, IC1 ... Comparison circuit, RPS...response circuit.
Claims (1)
間でデータ転送を行なうデータ転送装置において
、 前記データバスをアドレス及びデータを送受信
するアドレス・データバスと、アドレス・データ
の流れを制御する制御バスと、エラー検出線とで
構成し、前記各通信装置内に、内部バスと前記ア
ドレス・データバス上の各データを比較しエラー
検出を行ない当該エラー検出信号を前記エラー検
出線に出力する比較回路と、前記エラー検出線か
らの信号を入力しこのエラー検出線がアサートさ
れている時は応答を行なわないように構成した応
答回路とを設けたことを特徴とするデータ転送装
置。[Claims for Utility Model Registration] In a data transfer device that transfers data between two or more communication devices connected via a data bus, the data bus is an address data bus that transmits and receives addresses and data, and an address data bus that transmits and receives addresses and data. The communication device is configured with a control bus that controls the flow of data, and an error detection line, and in each communication device, errors are detected by comparing each data on the internal bus and the address/data bus, and the error detection signal is sent to the error detection line. Data characterized in that it is provided with a comparison circuit that outputs to the detection line, and a response circuit that inputs the signal from the error detection line and is configured not to respond when the error detection line is asserted. Transfer device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13875986U JPS6348254U (en) | 1986-09-10 | 1986-09-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13875986U JPS6348254U (en) | 1986-09-10 | 1986-09-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6348254U true JPS6348254U (en) | 1988-04-01 |
Family
ID=31044030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13875986U Pending JPS6348254U (en) | 1986-09-10 | 1986-09-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6348254U (en) |
-
1986
- 1986-09-10 JP JP13875986U patent/JPS6348254U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6348254U (en) | ||
| JPS63135436U (en) | ||
| JPS63175251U (en) | ||
| JPH03120149U (en) | ||
| JPH02123632U (en) | ||
| JPS6446840U (en) | ||
| JPS62109542U (en) | ||
| JPH03124202U (en) | ||
| JPS6339763U (en) | ||
| JPS61168444U (en) | ||
| JPS61192353U (en) | ||
| JPS6011547U (en) | modem | |
| JPH0223185U (en) | ||
| JPH0415743U (en) | ||
| JPS6368054U (en) | ||
| JPS6077149U (en) | signal transmission system | |
| JPS6363852U (en) | ||
| JPS6348249U (en) | ||
| JPS6335149U (en) | ||
| JPH0334148U (en) | ||
| JPH0288180U (en) | ||
| JPH0382441U (en) | ||
| JPS6087050U (en) | data transfer control device | |
| JPH0289545U (en) | ||
| JPS6214536U (en) |