JPS62109542U - - Google Patents

Info

Publication number
JPS62109542U
JPS62109542U JP1985202152U JP20215285U JPS62109542U JP S62109542 U JPS62109542 U JP S62109542U JP 1985202152 U JP1985202152 U JP 1985202152U JP 20215285 U JP20215285 U JP 20215285U JP S62109542 U JPS62109542 U JP S62109542U
Authority
JP
Japan
Prior art keywords
address
transmission
circuit
counter
counts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1985202152U
Other languages
Japanese (ja)
Other versions
JPH0326696Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985202152U priority Critical patent/JPH0326696Y2/ja
Publication of JPS62109542U publication Critical patent/JPS62109542U/ja
Application granted granted Critical
Publication of JPH0326696Y2 publication Critical patent/JPH0326696Y2/ja
Expired legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す構成ブロツク
図、第2図は第1図の装置の動作を説明する流れ
図、第3図、第4図は第1図の装置の動作を例示
するタイムチヤート、第5図は伝送装置全体の構
成ブロツク図、第6図は第5図の装置の動作説明
図、第7図は従来のマスタコントローラの構成ブ
ロツク図、第8図は第7図の装置の動作説明図で
ある。 11…アドレス発信回路、12…アドレスチエ
ツク回路、17…アドレスカウンタ、18…エラ
ーカウンタ。
FIG. 1 is a configuration block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of the device shown in FIG. 1, and FIGS. 3 and 4 illustrate the operation of the device shown in FIG. 1. Time chart, Fig. 5 is a block diagram of the entire transmission device, Fig. 6 is an explanatory diagram of the operation of the device in Fig. 5, Fig. 7 is a block diagram of the conventional master controller, and Fig. 8 is a block diagram of the structure of the device in Fig. 7. FIG. 3 is an explanatory diagram of the operation of the device. 11...Address transmission circuit, 12...Address check circuit, 17...Address counter, 18...Error counter.

Claims (1)

【実用新案登録請求の範囲】 ブランチに対応したアドレス信号を伝送路に送
信するアドレス発信回路と、 前記伝送路より送られたデータを読取る信号変
換回路と、 これらアドレス発信回路、信号変換回路及び前
記伝送路のエラーを検出するエラー検出回路 とを備えた多重伝送装置において、 上記アドレス発信回路が送信したアドレス数を
計数するアドレスカウンタと、 このアドレスカウンタの出力によつて初期化さ
れ、前記エラー検出回路が検出したエラーの数を
計数するエラーカウンタ とを設けたことを特徴とする多重伝送装置。
[Claims for Utility Model Registration] An address transmission circuit that transmits an address signal corresponding to a branch to a transmission line, a signal conversion circuit that reads data sent from the transmission line, these address transmission circuits, signal conversion circuits, and the above. In a multiplex transmission device equipped with an error detection circuit that detects errors in a transmission path, an address counter that counts the number of addresses transmitted by the address transmission circuit; and an address counter that is initialized by the output of this address counter, A multiplex transmission device comprising: an error counter that counts the number of errors detected by a circuit.
JP1985202152U 1985-12-25 1985-12-25 Expired JPH0326696Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985202152U JPH0326696Y2 (en) 1985-12-25 1985-12-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985202152U JPH0326696Y2 (en) 1985-12-25 1985-12-25

Publications (2)

Publication Number Publication Date
JPS62109542U true JPS62109542U (en) 1987-07-13
JPH0326696Y2 JPH0326696Y2 (en) 1991-06-10

Family

ID=31166264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985202152U Expired JPH0326696Y2 (en) 1985-12-25 1985-12-25

Country Status (1)

Country Link
JP (1) JPH0326696Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860846A (en) * 1981-10-06 1983-04-11 Nec Corp Detector for error in channel combination

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860846A (en) * 1981-10-06 1983-04-11 Nec Corp Detector for error in channel combination

Also Published As

Publication number Publication date
JPH0326696Y2 (en) 1991-06-10

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