JPS6347844A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6347844A
JPS6347844A JP61191362A JP19136286A JPS6347844A JP S6347844 A JPS6347844 A JP S6347844A JP 61191362 A JP61191362 A JP 61191362A JP 19136286 A JP19136286 A JP 19136286A JP S6347844 A JPS6347844 A JP S6347844A
Authority
JP
Japan
Prior art keywords
main memory
virtual
computer
value
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61191362A
Other languages
Japanese (ja)
Inventor
Koji Muramoto
村本 浩司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61191362A priority Critical patent/JPS6347844A/en
Publication of JPS6347844A publication Critical patent/JPS6347844A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To shorten an accessing time, by bypassing a virtual main memory conversion part when a virtual computer accesses to the specific area of a main memory in a real computer. CONSTITUTION:When the value of a flip-flop 4 is '0', in other words, when an address is the one where no accessing to a hardware area is performed, a selector 5 selects the output of an adder 2. Meanwhile, at the time of accessing to the hardware area, the selector 5 selects the value of a main memory address register 1 by setting the value of the flip-flop at '1'. Thereby, the address used in the accessing to a main memory device on the real computer goes to a value itself set at the main address register 1, regardless the value of a virtual main memory base register 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は情報処理装置に関し、特に仮想計算機の実現に
際しての主記憶装置のアドレスの生成技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a technique for generating addresses of a main storage device when realizing a virtual computer.

〔従来の技術〕[Conventional technology]

一般に仮想計算機の実現に際しては仮想計算機の主記憶
装置として実計算機の主記憶装置の一部が割り当てられ
ている。第2図にメモリマツプの一例を示す。第2図に
おいて実計算機のメモリアドレスは0〜1677721
5番地まであるがその一部すなわち12582912〜
16777215番地に仮想計算機の主記憶が割あてら
れている。そして仮想計算機上では上記範囲の主記憶に
対しO〜4194303番地のアドレスを付与している
。このため仮想計算機の主記憶アドレスと、対応する実
計算機上の主記憶アドレスとの間には一定の差があるた
め、仮想計算機の主記憶アドレスに一定値を加算するこ
とによって実計算機上の主記憶アドレスへの変換を行な
う必要がある。
Generally, when realizing a virtual computer, a part of the main storage of a real computer is allocated as the main storage of the virtual computer. FIG. 2 shows an example of the memory map. In Figure 2, the memory address of the real computer is 0 to 1677721.
There are up to number 5, but some of them are 12582912~
The main memory of the virtual machine is allocated to address 16777215. Then, on the virtual machine, addresses from 0 to 4194303 are assigned to the main memory in the above range. Therefore, since there is a certain difference between the main memory address of the virtual machine and the corresponding main memory address of the real computer, by adding a certain value to the main memory address of the virtual machine, the main memory address of the real computer is It is necessary to perform a conversion to a storage address.

従来の情報処理装置ではこの加算を自動的に行なう仮想
主記憶空間変換手段を備えることによって仮想計算機上
で実行される処理が仮想計算機であるか否かを意識する
必要がない様に構成されていた。第3図に示す仮想主記
憶空間変換部34がそれである。仮想計算機の主記憶ア
ドレスを実計算機の主記憶アドレスに変換する時に加算
値を仮想主記憶ペースレジスタ33に設定し、主記憶ア
ドレスレジスタ31に設定された仮想計算機上の主記憶
アドレスとこの加算値とを加算器32により自動的に加
算することによりこの加算は仮想計算機から意識する必
要のない様になっていた。
Conventional information processing devices are configured so that there is no need to be aware of whether processing executed on a virtual computer is a virtual computer or not by providing a virtual main memory space conversion means that automatically performs this addition. Ta. This is the virtual main memory space conversion unit 34 shown in FIG. When converting the main memory address of the virtual computer to the main memory address of the real computer, an added value is set in the virtual main memory pace register 33, and the main memory address on the virtual computer set in the main memory address register 31 and this added value are The adder 32 automatically adds the numbers, so that there is no need for the virtual computer to be aware of this addition.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述したように従来の情報処理装置では仮想主記憶空間
変換部は仮想計算機からの主記憶装置へのアクセスのす
べてに対して仮想計算機の主記憶アドレスに仮想主記憶
ペースレジスタ33の値が加算されてしまうため、実計
算機上の入出力装置等に関する情報を格納した第2図の
メモリマツプに示すハードウェア領域を仮想計算機中か
らアクセスする際には、前述の加・算が行なわれる事を
意識してあらかじめ補正を行ない、加算された後に正し
い値となる様に考慮するか、またはハードウェア領域へ
のアクセスを行なう時には仮想主記憶ペースレジスタの
値を0に変更し、アクセス終了後に再度正しい値に再設
定する必要があるため、ハードウェア領域へアクセスす
る際に処理速度が低下してしまうという欠点がある。
As described above, in the conventional information processing device, the virtual main memory space conversion unit adds the value of the virtual main memory pace register 33 to the main memory address of the virtual machine for every access to the main memory from the virtual machine. Therefore, when accessing the hardware area shown in the memory map in Figure 2 that stores information about input/output devices on the real computer from within the virtual computer, be aware that the above-mentioned additions and arithmetic operations will be performed. Either correct it in advance so that it will be the correct value after the addition, or change the value of the virtual main memory pace register to 0 when accessing the hardware area, and then change it to the correct value again after the access is completed. Since it is necessary to reconfigure the settings, there is a drawback that the processing speed decreases when accessing the hardware area.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の情報処理装置は、仮想計算機が走行している情
報処理装置において、走行中の前記仮想計算機に割り当
てられた実計算機の主記憶装置の主記憶空間の先頭アド
レスを保持する記憶手段と、前記記憶手段の出力と前記
仮想計算機上で行なわれる前記主記憶装置へのアクセス
に使用されるアドレスとを加算する加算手段と、前記実
計算機の主記憶装置の特定領域を前記仮想計算機がアク
セスすることを表示する表示手段と、前記表示手段の出
力により前記加算手段の出力と前記仮想計算機システム
上で行なわれる前記主記憶装置へのアクセスに使用され
るアドレスとのいずれか一方を選択する選択手段とを含
んで構成される。
An information processing device of the present invention includes, in an information processing device in which a virtual computer is running, a storage unit that holds a start address of a main storage space of a main storage device of a real computer allocated to the running virtual computer; addition means for adding the output of the storage means and an address used for accessing the main storage device performed on the virtual computer; and the virtual computer accesses a specific area of the main storage device of the real computer. a display means for displaying the information, and a selection means for selecting either the output of the addition means or the address used for accessing the main storage device on the virtual computer system based on the output of the display means. It consists of:

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の要部を示すブロック図であ
る。仮想主記憶空間変換部10は加算器2、仮想主記憶
ペースレジスタ3.およびセレクタ5から構成される。
FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. The virtual main memory space conversion unit 10 includes an adder 2, a virtual main memory pace register 3. and a selector 5.

加算器2は主記憶アドレスレジスタ1の出力と仮想主記
憶ペースレジスタ3の出力とを加算し、その出力はセレ
クタ5の一方の入力となっている。セレクタ5の他方の
入力には主記憶アドレスレジスタ1の出力がそのまま接
続されている。
Adder 2 adds the output of main memory address register 1 and the output of virtual main memory pace register 3, and the output serves as one input of selector 5. The output of the main memory address register 1 is directly connected to the other input of the selector 5.

実計算機の主記憶のハードウェア領域をアクセスするア
ドレスが主記憶アドレスレジスタ1に設定されたことを
表示するフリップフロップ4の値が“0″の時、すなわ
ちハードウェア領域をアクセスしないアドレスのときに
はセレクタ5は加算器2の出力を選択する。たとえば主
記憶アドレスレジスタ1の値が4,096で仮想主記憶
ペースレジスタ3の値が12,582,912(12X
2”=12M)の場合には実計算機上の主記憶装置への
アクセスに使用されるアドレスは12.587.008
となる。一方、ハードウェア領域へのアクセスを行なう
際にはフリップフロップの値を“1”にすることにより
セレクタ5は主記憶アドレスレジスタ1の値を選択する
。このため仮想主記憶ペースレジスタ3の値に関係なく
常に実計算機上の主記憶装置へのアクセスに使用される
アドレスは、上記の例では4,096となり、主記憶ア
ドレスレジスタ1に設定した値そのものが直接実計算機
上のアドレスとなる。
When the value of flip-flop 4, which indicates that the address that accesses the hardware area of the main memory of the real computer is set in main memory address register 1, is "0", that is, when the address does not access the hardware area, the selector 5 selects the output of adder 2. For example, the value of main memory address register 1 is 4,096 and the value of virtual main memory pace register 3 is 12,582,912 (12X
2”=12M), the address used to access the main memory on the actual computer is 12.587.008.
becomes. On the other hand, when accessing the hardware area, the selector 5 selects the value of the main memory address register 1 by setting the value of the flip-flop to "1". Therefore, regardless of the value of virtual main memory pace register 3, the address always used to access the main memory on the real computer is 4,096 in the above example, which is the same value set in main memory address register 1. becomes the address directly on the real computer.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明には、実計算機の主記憶の特
定領域に仮想計算機がアクセスするときには仮想主記憶
変換部をバイパスすることにより従来に比しアクセス時
間を短縮できるという効果がある。
As explained above, the present invention has the effect that when a virtual machine accesses a specific area of the main memory of a real computer, the access time can be shortened compared to the conventional art by bypassing the virtual main memory converter.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
仮想計算機における主記憶アドレスと実計算機における
主記憶アドレスとの対応を示すメモリマツプ図、第3図
は従来例のブロック図である。 1.31・・・主記憶アドレスレジスタ、2.32・・
・加算器、3,33・・・仮想主記憶ベースレージスタ
、4・・・フリップフロップ、5・・・セレクタ、10
゜34・・・仮想主記憶空間変換部。 代理人 弁理士 内 原 ゛、晋 第1図 第2図 第3図
Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a memory map diagram showing the correspondence between main memory addresses in a virtual machine and main memory addresses in a real computer, and Figure 3 is a block diagram of a conventional example. be. 1.31...Main memory address register, 2.32...
- Adder, 3, 33... Virtual main memory base register, 4... Flip-flop, 5... Selector, 10
゜34...Virtual main memory space conversion unit. Agent Patent Attorney Susumu Uchihara Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 仮想計算機が走行している情報処理装置において、走行
中の前記仮想計算機に割り当てられた実計算機の主記憶
装置の主記憶空間の先頭アドレスを保持する記憶手段と
、前記記憶手段の出力と前記仮想計算機上で行なわれる
前記主記憶装置へのアクセスに使用されるアドレスとを
加算する加算手段と、前記実計算機の主記憶装置の特定
領域を前記仮想計算機がアクセスすることを表示する表
示手段と、前記表示手段の出力により前記加算手段の出
力と前記仮想計算機システム上で行なわれる前記主記憶
装置へのアクセスに使用されるアドレスとのいずれか一
方を選択する選択手段とを含むことを特徴とする情報処
理装置。
In an information processing device on which a virtual computer is running, a storage means for holding the start address of a main memory space of a main storage device of a real computer allocated to the running virtual machine, and an output of the storage means and the virtual an addition means for adding an address used for access to the main storage device performed on a computer; a display means for displaying that the virtual computer is accessing a specific area of the main storage device of the real computer; The present invention is characterized by comprising a selection means for selecting either the output of the addition means or an address used for accessing the main storage device performed on the virtual computer system based on the output of the display means. Information processing device.
JP61191362A 1986-08-15 1986-08-15 Information processor Pending JPS6347844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61191362A JPS6347844A (en) 1986-08-15 1986-08-15 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61191362A JPS6347844A (en) 1986-08-15 1986-08-15 Information processor

Publications (1)

Publication Number Publication Date
JPS6347844A true JPS6347844A (en) 1988-02-29

Family

ID=16273315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61191362A Pending JPS6347844A (en) 1986-08-15 1986-08-15 Information processor

Country Status (1)

Country Link
JP (1) JPS6347844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000051005A1 (en) * 1999-02-23 2000-08-31 Hitachi, Ltd. Integrated circuit and information processing device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57189386A (en) * 1981-05-18 1982-11-20 Hitachi Ltd Information processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57189386A (en) * 1981-05-18 1982-11-20 Hitachi Ltd Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000051005A1 (en) * 1999-02-23 2000-08-31 Hitachi, Ltd. Integrated circuit and information processing device

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