JPS5817993B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus equipped with a virtual address to real address translation device.

Conventionally, address translation devices in this type of information processing equipment do not maintain spatial representations of tasks that the channel program or central processing unit attempts to execute. Each time the spatial representation of a task changes, a completely new real address translation must be performed, which has the drawback of significantly impairing the address translation and main memory access efficiency.

An object of the present invention is to provide an information processing device that solves the above-mentioned drawbacks.

More specifically, as a spatial representation of the task that the channel program or central processing unit is trying to execute, the progress of the virtual address/real address conversion that will be executed halfway is displayed as a spatial representation of the task that the channel program or central processing unit is trying to execute. By storing the data in advance of the execution of the task that the device is about to execute, it reduces the number of execution steps conventionally required for real address translation, improves the main memory access efficiency of the address translation device, and eliminates the need for real address translation requests. It is an object of the present invention to provide an information processing device that can quickly convert an address into a real address at the time the address is received.

In order to achieve the above object, an information processing device according to the present invention stores control information for each channel as a table in a main storage device, and has a virtual address space display that displays a virtual address space of a channel program specified by a virtual address. In the information processing device provided in the control information, an address translation device that converts the virtual address into a real address, and a central processing unit virtual that stores one or more virtual address space representations of tasks that the central processing unit intends to execute. an address space representation; one or more channel virtual address space representations for storing the virtual address space representations read from the main memory when the channel attempts to execute the channel program; and the central processing unit. The control device includes a virtual address space display device and a control device that selects a virtual address space display shown by the channel virtual address space display device and inputs the selected virtual address space display to the address translation device.

According to the above configuration, the above object can be completely achieved.

The present invention will be described in more detail below with reference to the drawings.

In this embodiment, tasks executed by a central processing unit (referred to as CPU), transfer data required by a channel program, or communication between the CPU and the channel program are all managed by processes and process groups.

The process exists for each task visible to the software, and the latest information regarding the process is always managed by the process control block that exists for each process.

Therefore, in order for a task to be executed by the CPU or a channel program to obtain the main memory address necessary for transfer data, the task to be executed by the CPU or a channel program must be stored in the process control block corresponding to the related task of the channel program. It is necessary to obtain an address space indicator word used to obtain the first address on the main memory of each of the tasks currently in use.

Next, using FIG. 1, the process control block 15
The process of accessing the PCB (referred to as PCB) will be explained.

Access to the PCB 15 is via the boundary address register 11.
By reading the contents of , the start address of the system base 12 is known.

Then, the 5-table pointer and process names (denoted as J and P), which are virtual space display information in the system base, are extracted.

The 5-table pointer is the start address of 5-table 13.

5 Table 13 provides entries for every job step currently in the system.

Each entry in 5-table 13 contains a 2-table pointer.

The 2-table pointer is the start address of the P-table 14.

Each entry in P table 14 contains a PCB pointer, pointing to the starting address of PCB 15.

By adding the 5-table pointer obtained from the system base 12 and the J number of the process, the 1-table entry for the job step to which the process belongs is determined.

Next, the P number of the process is added to the 2-table pointer in the 5-table entry to obtain the 2-table entry for that process.

The PCB pointer of the process is obtained from this 2-table entry, and is used to access the PCB.

The ASW 16 in the PCB 15 is used to access a segment desired as a real address, that is, a logical block containing data or instruction code.

Next, the operation of the present invention will be described.

As mentioned above, virtual address/real address conversion in this embodiment requires a very large number of main memory accesses.

Therefore, by retaining the address space information J, P, and ASW of the process related to the CPU program or channel program that requires the address translation request in advance of the real address translation request, the real address translation request can be made later. When , the real address translation is
Address translation is only performed from the retained J, P, and ASW, thereby substantially shortening the address translation process.

For this purpose, in this embodiment, a JP buffer 25 and an ASW buffer 26 corresponding to the JP buffer are provided.

The control device 24 obtains the ASW from the J and P through L1 to L4 in FIG.
Write to buffer 25 and ASW buffer 26.

Regarding its execution, the control device 24 includes a CPU program and a channel program processing function. Therefore, the use of each of the buffers in common for these processes is limited to when writing J, P, and ASW in other processes, or when writing an address. J, P and A already written in the buffer at the time of conversion request
Requires SW evacuation and recovery time.

Therefore, in this embodiment, the J, P, and ASW are stored in the central processing unit virtual address space display device 22 or the channel virtual address space display device 23 according to the execution order of the control device 24 for each CPU program and channel program process. Write to JP buffer 25 and ASW buffer 26.

Here, when the CPU program and the channel program are divided into a plurality of execution sections, a plurality of the JP buffers 25 and ASW buffers 26 may exist depending on the execution section of each program.

Therefore, the real address translation by the real address translation request from the control device 24 to the address translation device 21 is limited to the translation path after the ASW 16 in the PCB 15 in FIG.

In this embodiment, the CPU program and the channel program are processed by the same control circuit, but the present invention is also effective in a system in which these programs are controlled independently of each other.

[Brief explanation of the drawings] Figure 1 shows part of the real address conversion step? FIG. 2 is a diagram showing an embodiment of the present invention. 11...BAR (boundary display register), 12.
...-System pace, 13...5 tables, 1
4... P table, 21... Address translation device, 22... Central processing unit virtual address space display device, 23... Channel virtual address space display device , 24...control device, 25...
JP buffer, 26...ASW buffer.

Claims (1)

[Claims] 1. An information processing device that stores control information for each channel as a table in a main storage device and is provided with a virtual address space display in the control information that displays a virtual address space of a channel program specified by a virtual address. one or more central processing unit virtual address space representations for storing virtual address space representations of tasks that the central processing unit intends to execute; one or more channel virtual address space display devices for storing the virtual address space representations read from the main memory when the central processing unit virtual address space display device and the channel virtual address space display device An information processing apparatus characterized in that the information processing apparatus is configured to select a virtual address space display indicated by and input it to the address translation apparatus.