JPS6347845A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6347845A
JPS6347845A JP61191363A JP19136386A JPS6347845A JP S6347845 A JPS6347845 A JP S6347845A JP 61191363 A JP61191363 A JP 61191363A JP 19136386 A JP19136386 A JP 19136386A JP S6347845 A JPS6347845 A JP S6347845A
Authority
JP
Japan
Prior art keywords
main memory
value
virtual
computer
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61191363A
Other languages
Japanese (ja)
Inventor
Koji Muramoto
村本 浩司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61191363A priority Critical patent/JPS6347845A/en
Publication of JPS6347845A publication Critical patent/JPS6347845A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To shorten an accessing time, by switching an addition value to a specific value when a virtual computer accesses to the specific area of a main memory in a real computer. CONSTITUTION:When a flip-flop 4 is set at '0', namely, when an address set at a main memory address register 1 is the one that does not access to a hardware, a selector 5 selects a virtual main memory base register 3. In other words, the value of the virtual main memory base register 3 is added on the output of the main memory address register 1 at this time. Meanwhile, at the time of being accessed to the hardware area, it follows that the selector 5 selects a value '0' of a fixed value generation circuit 6 by setting the value of the flip-flop 4 at '1', and the address to be used for the accessing to a main memory device on the real computer always goes to the value set at the main memory address register 1 regardless the value of the virtual main memory base register 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は情報処理装置に関し、特に仮想計算機の実現に
際して主記憶装置のアドレスの生成技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a technique for generating addresses of a main storage device when realizing a virtual computer.

〔従来の技術〕[Conventional technology]

一般に仮想計算機の実現に際しては、仮想計算機の主記
憶装置として実計算機め主記憶装置の一部が割り当てら
れている。第2図にメモリマツプの一例を示す。第2図
において実計算機のメモリアドレスはO〜167772
15番地まであるが、その一部すなわち1258291
2〜16777215番地に仮想計算機の主記憶が割あ
てられている。そして仮想計算機上では上記範囲の主記
憶に対しO〜4194303番地のアドレスを付与して
いる。このため仮想計算機の主記憶アドレスと、対応す
る実計算機上の主記憶アドレスとの間には一定の差があ
るため、仮想計算機の主記憶アドレスに一定値を加算す
ることによって実計算機上の主記憶アドレスへの変換を
行なう必要がある。
Generally, when realizing a virtual computer, a part of the main storage of the real computer is allocated as the main storage of the virtual computer. FIG. 2 shows an example of the memory map. In Figure 2, the memory address of the real computer is O~167772.
There are up to number 15, but part of it is 1258291.
The main memory of the virtual machine is allocated to addresses 2 to 16777215. Then, on the virtual machine, addresses from 0 to 4194303 are assigned to the main memory in the above range. Therefore, since there is a certain difference between the main memory address of the virtual machine and the corresponding main memory address of the real computer, by adding a certain value to the main memory address of the virtual machine, the main memory address of the real computer is It is necessary to perform a conversion to a storage address.

従来の情報処理装置ではこの加算を自動的に行なう仮想
主記憶空間変換手段を備える・ことによって仮想計算機
上で実行される処理が仮想計算機であるか否かを意識す
る必要ない様に構成されていた。第3図に示す仮想主記
憶空間変換部34がそれである。仮想計算機の主記憶ア
ドレスを実計算機の主記憶アドレスに変換する時に加算
値を仮想主記憶ペースレジスタ33に設定し主記憶アド
レスレジスタ31に設定された仮想計算機上の主記憶ア
ドレスとこの加算値とを加算器32により自動的に加算
することによりこの加算は仮想計算機から意識する必要
のない様になっていた。
Conventional information processing devices are equipped with a virtual main memory space conversion means that automatically performs this addition, so that there is no need to be aware of whether the processing executed on the virtual machine is a virtual machine or not. Ta. This is the virtual main memory space conversion unit 34 shown in FIG. When converting a main memory address of a virtual computer to a main memory address of a real computer, an added value is set in the virtual main memory pace register 33, and the main memory address on the virtual computer set in the main memory address register 31 is combined with this added value. is automatically added by the adder 32, so that the virtual computer does not need to be aware of this addition.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述したように従来の情報処理装置では仮想主記憶空間
変換部は仮想計算機からの主記憶装置へのアクセスのす
べてに対して仮想計算機の主記憶アドレスに仮想主記憶
ペースレジスタ33の値を加算してしまうため、実計算
機上の入出力装置等に関する情報を格納した第2図のメ
モリマツプに示すハードウェア領域を仮想計算機中から
アクセスする際には、前述の加算が行なわれる事を意識
してあらかじめ補正を行ない、加算された後に正しい値
となる様に考慮するか、またはハードウェア領域へのア
クセスを行なう時には仮想主記憶ペースレジスタの値を
Oに変更してアクセス終了後に再度圧しい値に再設定す
る必要があるため、ハードウェア領域へアクセスする際
に処理速度が低下してしまうという欠点がある。
As described above, in the conventional information processing device, the virtual main memory space conversion unit adds the value of the virtual main memory pace register 33 to the main memory address of the virtual machine for every access to the main memory from the virtual machine. Therefore, when accessing the hardware area shown in the memory map in Figure 2 that stores information about input/output devices on the real computer from within the virtual computer, be aware that the above-mentioned addition will be performed in advance. Make corrections so that the correct value is obtained after the addition, or change the value of the virtual main memory pace register to O when accessing the hardware area and reset it to the overwhelming value after the access is completed. Since the settings need to be made, the disadvantage is that the processing speed decreases when accessing the hardware area.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の情報処理装置は、仮想計算機が走行している情
報処理装置において、走行中の前記仮想計算機に割り当
てられた実計算機の主記憶装置の主記憶空間の先頭アド
レスを保持する記憶手段と、あらかじめ設定された固定
値を発生する固定値発生手段と、前記実計算機の主記憶
装置の特定領域を前記仮想計算機がアクセスすることを
表示する表示手段と、前記表示手段の出力により前記記
憶手段と前記固定値発生手段とのいずれか一方3遷釈す
る選択手段と、前記選択手段の出力と前記仮想計算機シ
ステム上で行なわれる前記主記憶装置へのアクセスに使
用されるアドレスとを加算する加算手段とを含んで構成
される。
An information processing device of the present invention includes, in an information processing device in which a virtual computer is running, a storage unit that holds a start address of a main storage space of a main storage device of a real computer allocated to the running virtual computer; fixed value generating means for generating a preset fixed value; display means for displaying that the virtual computer is accessing a specific area of the main storage of the real computer; a selection means for translating one of the fixed value generation means three times; and an addition means for adding the output of the selection means and an address used for accessing the main storage device on the virtual computer system. It consists of:

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の要部を示すブロック図であ
る。仮想主記憶空間変換部10は加算器2、仮想主記憶
ペースレジスタ3.セレクタ5゜固定値発生回路6から
成り、実計算機の主記憶のハードウェア領域をアクセス
°するアドレスが主記憶アドレスレジスタ1に設定され
たことを表示するフリップフロップ4によりセレクタ5
は仮想主記憶ペースレジスタ3と固定値発生回路6のい
ずれが一方を選択する。固定値発生回路6は数値“0”
を発生する。
FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. The virtual main memory space conversion unit 10 includes an adder 2, a virtual main memory pace register 3. The selector 5 consists of a fixed value generation circuit 6, and the selector 5 is activated by a flip-flop 4 which indicates that the address for accessing the hardware area of the main memory of the actual computer has been set in the main memory address register 1.
Which of the virtual main memory pace register 3 and the fixed value generation circuit 6 selects one. Fixed value generation circuit 6 is a numerical value “0”
occurs.

セレクタ5はフリップフロップ4が0の時すなわち主記
憶アドレスレジスタ1にセットされたアドレスがハード
ウェア領域をアクセスしないアドレスのときは、仮想主
記憶ペースレジスタ3を選択する。すなわちこの時には
主記憶アドレスレジスタ1の出力に仮想主記憶ペースレ
ジスタ3の値が加算される。たとえは主記憶アドレスレ
ジスタ1の値が4,096で仮想主記憶ペースレジスタ
3の値が12.582,912 (12x220=12
M)の場合には実計算機上の主記憶装置へのアクセスに
使用されるアドレスは12,587,008となる。一
方、ハードウェア領域へのアクセスを行なう際にはフリ
ップフロップブ4の値を“1”にすることによりセレク
タ5は固定値発生回路6の値“O”を選択することとな
り、仮想主記憶ペースレジスタ3の値に関係なく常に実
計算機上の主記憶装置へのアクセスに使用されるアドレ
スは、上述の例では4,096となる。
The selector 5 selects the virtual main memory pace register 3 when the flip-flop 4 is 0, that is, when the address set in the main memory address register 1 is an address that does not access the hardware area. That is, at this time, the value of the virtual main memory pace register 3 is added to the output of the main memory address register 1. For example, the value of main memory address register 1 is 4,096 and the value of virtual main memory pace register 3 is 12.582,912 (12x220=12
In case M), the address used to access the main memory on the actual computer is 12,587,008. On the other hand, when accessing the hardware area, by setting the value of the flip-flop block 4 to "1", the selector 5 selects the value "O" of the fixed value generation circuit 6, and the virtual main memory In the above example, the address that is always used to access the main memory on the actual computer, regardless of the value of register 3, is 4,096.

本実施例は固定値が0の場合について説明したが本発明
はこれに限るものでなくハードウェア領域すなわち主記
憶の特定領域に対応して特定固定値であれはよい。
Although this embodiment has been described with reference to the case where the fixed value is 0, the present invention is not limited to this, and any specific fixed value corresponding to a specific area of the hardware area, that is, the main memory may be used.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、実計算機の主記憶の特定領域に仮
想計算機がアクセスするときには加算値を特定の値に切
換えることにより従来に比しアクセス時間を短縮できる
という効果がある。
As explained above, when a virtual computer accesses a specific area of the main memory of a real computer, switching the addition value to a specific value has the effect of shortening the access time compared to the conventional method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
仮想計算機における主記憶アドレスと実計算機における
主記憶アドレスとの対応を示すメモリマツプ図、第3図
は従来例のブロック図である。 1.31・・・主記憶アドレスレジスタ、2.32・・
・加算器、3.33・・・仮想主記憶ペースレジスタ、
4・・・プリップフロップ、5・・・セレクタ、6・・
・固定値発生回路、10.34・・・仮想主記憶空間変
換部。 ・−で 代理人 弁理士 内 原  ・晋 イt’4NI機に一+実tf*ヰ砲1」;ntf14t
アトしλ   主記+tアトしス第2図 第3図
Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a memory map diagram showing the correspondence between main memory addresses in a virtual machine and main memory addresses in a real computer, and Figure 3 is a block diagram of a conventional example. be. 1.31...Main memory address register, 2.32...
・Adder, 3.33...virtual main memory pace register,
4...Pre-flop, 5...Selector, 6...
-Fixed value generation circuit, 10.34...virtual main memory space conversion unit.・-Representative Patent Attorney Uchihara ・Shinichi t'4NI aircraft 1 + real TF * 1 gun"; ntf14t
Atoshi λ Main note + t Atoshisu Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 仮想計算機が走行している情報処理装置において、走行
中の前記仮想計算機に割り当てられた実計算機の主記憶
装置の主記憶空間の先頭アドレスを保持する記憶手段と
、あらかじめ設定された固定値を発生する固定値発生手
段と、前記実計算機の主記憶装置の特定領域を前記仮想
計算機がアクセスすることを表示する表示手段と、前記
表示手段の出力により前記記憶手段と前記固定値発生手
段とのいずれか一方を選択する選択手段と、前記選択手
段の出力と前記仮想計算機システム上で行なわれる前記
主記憶装置へのアクセスに使用されるアドレスとを加算
する加算手段とを含むことを特徴とする情報処理装置。
In an information processing device on which a virtual computer is running, a storage means for holding a start address of a main storage space of a main storage device of a real computer allocated to the running virtual computer, and generating a preset fixed value. a fixed value generation means for displaying that the virtual computer is accessing a specific area of the main storage of the real computer; Information characterized in that it includes a selection means for selecting either one, and an addition means for adding an output of the selection means and an address used for accessing the main storage device performed on the virtual computer system. Processing equipment.
JP61191363A 1986-08-15 1986-08-15 Information processor Pending JPS6347845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61191363A JPS6347845A (en) 1986-08-15 1986-08-15 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61191363A JPS6347845A (en) 1986-08-15 1986-08-15 Information processor

Publications (1)

Publication Number Publication Date
JPS6347845A true JPS6347845A (en) 1988-02-29

Family

ID=16273331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61191363A Pending JPS6347845A (en) 1986-08-15 1986-08-15 Information processor

Country Status (1)

Country Link
JP (1) JPS6347845A (en)

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