JPH01201748A - Data processor - Google Patents

Abstract

PURPOSE:To shorten execution time by holding the corresponding sum value of all constant values and all the combinations of plural registers for generating addresses by a specific number or above of address registers and using one content in the address registers when executing a memory access. CONSTITUTION:A base register 11 for generating addresses and two index registers 12 and 13 are provided and when executing a machine language instruc tion, the constant values in the instruction is held by an instruction register 14. Address registers 16 to the number or above that the number of all the combinations of the register 12 and 13 and the number twice as large as the maximum value which the constant values can take are multiplied together are provided. The register 16 holds the corresponding sum value of all values that the constant value can take and all the combinations of the register 12 and 13 and when executing the memory access, one contents in the registers 16 is selected by a multiplexer 17 and used as address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that prepares address values during memory access.

[Prior Art] Conventionally, this type of data processing device has a plurality of address generation registers such as a pace register and an index register necessary for calculating an address value after starting execution of a machine language instruction that requires memory access. After reading the register, the sum with the constant value in the R machine instruction was calculated, and the result was given to the memory as an address.

[Problem to be Solved by the Invention] Therefore, in a conventional data processing device, from the start of execution of a machine language instruction until the actual start of memory access, multiple address generation registers are read and addresses are generated. This method requires time for calculation, which has the disadvantage that the execution time of the machine language instruction becomes correspondingly longer.

[Means for Solving the Problems] A data processing device according to the present invention includes a central processing unit that executes a machine language instruction and a memory, and when the machine language instruction is executed, the memory is connected to the central processing unit. In a device that uses the sum of contents held in a plurality of address generation registers in the central processing unit and a constant value included in the machine language instruction as an address to be accessed by the CPU, all of the plurality of address generation registers are used. The number of address registers is equal to or greater than the number of combinations of the constant value multiplied by twice the maximum value that the constant value can take, and the address register is configured to combine all the possible values of the constant value and the plurality of addresses. It is characterized in that it holds the corresponding sum value of all combinations of generation registers, and uses the contents of one selected from the address registers as an address when performing memory access.

[Operation] Since the address register holds the corresponding sum value of all possible values of the constant value and all combinations of multiple address generation registers, when executing memory access,
It is possible to eliminate the need to calculate the value of the address in the execution start word of the A language instruction that requires memory access, and it is possible to shorten the execution time of the machine language instruction.

[Examples] Examples of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, a data processing device according to an embodiment of the present invention includes a right central processing unit (hereinafter referred to as a right central processing unit) that executes machine language instructions.
It has a CPU (abbreviated as CPU) 10 and a memory 20. CPU
l0 has a pace register 11 for address generation and two index registers 12.13. Constant values in machine language instructions are held in the instruction register 14 at the start of execution. Selection of index registers 12,13 is also performed by multiplexer 15 using index selection bit IDX in instruction register 14. If these sums are used as addresses and the range of constant values is -3 to +3, 14 combinations are possible. These 14 combinations are held in 14 address registers 16, respectively. The selection of these 14 address registers 16 is performed by multiplexer 17 using index selection bit IDX in instruction register 14 and constant values. Note that 18 is an adder, and there are the same number of adders as there are address registers 16.

When attempting to execute a machine language instruction that involves memory access, in the conventional case, there is no address register 16, as shown in FIG. It takes time. On the other hand, in the case of the present invention with the address register 16, as shown in FIG. 2(b), this time is not necessary, and I! Machine language instruction execution time becomes shorter.

The operation of this embodiment will be explained below.

For example, suppose that the constant value in the machine language instruction is -2'' and the index register 11 is selected by the index selection bit IOX.At this time, from the constant part in the instruction register 14, the “B
One address register in which the value “+R1-2” is stored is selected. Here, B is the content of the pace register 11, and R1 is the content of the index register 11.
The index register 12 stores R2.

Similarly, when the constant value is "0", the address register storing the value "B+R1" is selected. This timing is the same as the time when the machine language instruction is stored in the instruction register 14, that is, the time when the execution of the machine language instruction starts. Therefore, as shown in FIG. 2(b), the address calculation time is No longer needed.

[Effects of the Invention] As explained above, according to the present invention, by providing an address register that holds the sum of the contents held in the address generation register and the constant value in the machine language instruction, address calculation is improved. This has the effect that the execution time of an R language instruction that requires memory access can be shortened to the extent that time is no longer required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data processing device according to an embodiment of the present invention, FIG. 2(a) is a diagram showing processing contents and execution time of machine language instructions in the conventional case, and FIG.
) is a diagram showing the processing contents and execution time of machine language instructions in the case of the present invention. 10... Central processing unit (CPU), 11... Pace register, 12.13... Index register, 1
4...Instruction register, 15...Multiplexer, 1
6... Address register, 17... Multiplexer, 18... Adder, 20... Memory. Broom 1 diagram

Claims (1)

[Claims] 1. A data processing device having a central processing unit that executes a machine language instruction and a memory, wherein when the machine language instruction is executed, the memory is accessed by the central processing unit as an address, and a plurality of addresses in the central processing unit are used. In a device that uses the sum of the contents held in address generation registers and a constant value included in the machine language instruction, the total number of combinations of the plurality of address generation registers and 2 of the maximum possible value of the constant value the number of address registers is equal to or greater than the number multiplied by the number of address registers, and the address registers have a corresponding sum value of all possible values of the constant value and all combinations of the plurality of address generation registers. 1. A data processing device, wherein the data processing device retains one of the address registers, and uses the contents of one of the address registers as an address when performing memory access.