JPH01263829A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the executing time of a machine word instruction requiring a memory access by calculating an address within a CPU from the sum of the contents of a base register and a constant contained in the machine word instruction. CONSTITUTION:A CPU 100 contains a base register 2 for generation of addresses and the constant value contained in a machine word instruction is held into an instruction register 1 at the start of execution. The sum of the contents of the register 2 and said constant value is held by an address register 6 and is used as an address. When the constants are obtained in a (-7 to +7) range, 15 different combinations, i.e., (BR +7 to BR -7) are available. In case a machine word instruction requiring an access is carried out and the register 6 is not available, the address calculating time is required before execution of a memory access. However said address calculating time can be omitted with use of the register 6. As a result, the time required for execution of the machine word instruction is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a device i1i that prepares an address at the time of memory access. Regarding the equipment to be prepared.

(Prior Art) Conventionally, this type of device starts execution of a machine language instruction that requires memory access, and then executes one machine language instruction after reading the contents of a pace register necessary to calculate the entire address value. The sum of the constant inside and the contents of the pace register was calculated, and the result was given to memory as an address.

(Problem to be solved by the invention) The conventional data processing device described above has problems from the start of execution of one machine language instruction to the time when memory access actually starts.
Since it takes time to read all the contents of the register and calculate the address, there is a drawback that the execution time of the above instruction becomes correspondingly longer.

An object of the present invention is to provide a plurality of address registers for holding the entire sum of the contents of the pace register and an integer value as a constant in m machine language instructions. Is it provided within the central processing unit and the address within the central processing unit? It is an object of the present invention to provide a data processing bag fi1' that eliminates all of the above-mentioned drawbacks through calculation and is configured so that the execution time of the mission statement does not become long.

(Means for Solving the Problems) A data processing device according to the present invention is capable of executing machine language instructions and is equipped with a central processing unit and a memory, and the central processing unit has (2n+1) ( n: integer value)
The system is equipped with an adder and an address register.

(2n+1) adders are used to calculate the sum of the contents held in the pace register and the integer n included in the machine language instruction when executing one machine language instruction, and generate a memory access address. It is.

The address register is for holding addresses generated by '(2n+1) adders.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a 1072 diagram showing an embodiment of a data processing device according to the present invention.

In FIG. 1, 1 is an instruction register, 2 is a pace register, 3 to 5 are adders, 6 is an address register,
7 is multiplexer% 100 is central processing bag [,200
is memory.

It is assumed that a pace register 2 for address generation is provided in the central processing bag fItioo, and a constant value in one machine language instruction is held in the instruction register 1 at the start of execution. If we use the sum of these as an address and assume that the constant (integer) value ranges from -7 to +7, then BR+7
- 15 combinations of BR-7 are possible. these 15
t-, and is held in the address register 6.

When attempting to execute a machine language instruction that involves memory access, if there is no address register 6, time is required for address calculation before memory access, as shown in FIG. 6, as shown in FIG. 2(b), this time becomes unnecessary and the execution time of the machine language instruction becomes shorter.

In this case, the operation is as follows.

For example, if the constant (integer) in the machine language instruction is -2, BR-2 of address register 6 is selected from the constant part of instruction register l, and when the constant is 0, B
R is selected.

In these cases, the contents of the address register 6 are selected at the same time as the machine language instruction is stored in the instruction register 1, that is, at the same time as the execution of the machine language instruction starts, and as shown in FIG. 2(b), there is no need for address calculation time. becomes.

(Effects of the Invention) As explained above, the present invention provides an address register in the central processing unit for holding the sum of the contents of the pace register and an integer as a constant in a machine language instruction, and the central processing unit By calculating the address within the program, the execution time of machine language instructions that require memory access can be reduced by the amount of time required to calculate the address.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. FIG. 2 is an explanatory diagram showing the relationship between processing contents of machine language instructions and execution time. 1...Instruction register 2...Pace register 3-5...Adder 6...Address register 7...Multiplexer 100...Central processing unit 200...Memory patent applicant NEC Corporation

Claims (1)

[Claims] A data processing device capable of executing machine language instructions and equipped with a central processing unit and a memory, wherein the central processing unit processes the contents held in a base register and the contents contained in the machine language instructions when executing the machine language instructions. (2n+1) adders for calculating the sum of a plurality of integer values n and generating access addresses for the memory; and (2n+1) adders for holding the addresses generated by the (2n+1) adders. 1. A data processing device comprising an address register.