JPH04160634A - Memory control device - Google Patents

Abstract

PURPOSE:To properly and economically execute slow and fast processing of programs by providing a memory control device with the 1st ROM for storing a program requiring fast processing at real time and the 2nd ROM for storing a program to be processed at a low speed and individually controlling these ROMs in accordance with respective purposes. CONSTITUTION:The memory control device is provided with a 1st fixed storage device 2 for storing a program requiring fast processing at real time, a 1st control means 3 for controlling the reading of the device 2, a 2nd fixed storage device 4 for storing a program to be processed at a low speed, a 2nd control means 5 for controlling the reading of the device 4, and a wait control means 6 for controlling the formation and sending of waiting states of the 1st and 2nd control means 3, 5 so as to access the devices 2, 4. Namely, the rapid ROM 2 and the slow ROM 4 can be properly used in accordance with respective purposes. Thus, the slow and fast processing of the programs can be properly and economically executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control device used in an information processing system.

[Conventional technology]

Conventionally, in a memory control device operated by a program by a processor, real-time operation of high-speed processing and operation of a diagnostic program, for example, which requires low-speed processing, are performed by the same fixed storage device (ROM) 9 as shown in FIG. Usually, a low-speed ROM is used and a wait is applied in the ROM control circuit 10 to reduce the processing speed. Further, a high-speed ROM can also be used as the ROM 9.

[Problem to be solved by the invention]

As mentioned above, in conventional memory control devices, real-time processing programs, diagnostic programs, and initial setting programs are usually input into the same low-speed ROM, so it is necessary to add a weight to the real-time processing program that is desired to perform high-speed processing. I had no choice but to use it at a slower processing speed.

Further, even if a high-speed ROM is used, the diagnostic program and the initial setting program can be processed at low speed, the ROM uses a large area, and is used infrequently. Therefore, if all the devices are configured as high-speed ROM'''C' and the memory capacity is the same, there is a drawback that the price and power consumption increase.

An object of the present invention is to provide a memory control device that can appropriately and economically perform low-speed and high-speed processing of programs.

[Means to solve the problem]

The memory control device of the present invention includes a first fixed storage device containing a program that requires high-speed processing in real time;
a first control means for controlling the continuous storage of the fixed storage device; a second fixed storage device containing a low-speed processing program;
a second control means for controlling reading of the second fixed storage device; and generating weights for the first and second control means to enable the processor to access the first and second fixed storage devices. This configuration also includes a weight control means for controlling transmission.

〔Example〕

Next, one embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, a memory control device 1 includes a high-speed ROM 2 connected to a processor 7 and containing a real-time processing program, and a high-speed ROM control circuit 3 that controls reading of the high-speed ROM 2. , low-speed ROM4 containing diagnostic programs and initial setting programs, and low-speed R
, a low-speed ROM control circuit 5 that performs read control of OM4, and 2
The weight control circuit 6 controls the weight of each type. High speed ROM2 and low speed ROM shown in FIG.
4 is divided into ROMs that perform real-time operations and perform high-speed processing, and ROMs that require low-speed processing such as diagnostic operations. Therefore, when performing high-speed processing, by using a high-speed ROM, unnecessary power consumption can be avoided and the configuration can be made more economical than when using low-speed R and OM and having the same memory capacity.

The operation will be explained below. The processor 7 uses address information via a data bus and an address bus to
OM, that is, high speed ROM2 and low speed ROM4 are accessed. When accessing high-speed ROM2, high-speed RO
The M control circuit 3 controls high-speed processing operations. Also,
When accessing the low-speed ROM 4, the low-speed ROM control circuit 5 controls the operation of low-speed processing. The wait control circuit 6 includes a high speed ROM control circuit 3 and a low speed ROM control circuit 5.
Controls the operation of generating and sending out weights. Further, the wait control circuit 6 is configured so that the memory in use is a high-speed ROM.
2 or low-speed ROM 5 based on the address information, and notifies the processor 7 of a control signal such as a signal indicating the completion of data transmission/reception preparation.

〔Effect of the invention〕

As explained above, the present invention provides a first ROM that contains a program that requires high-speed processing in real time and a second ROM that contains a program that requires low-speed processing, and controls them separately according to the purpose. This has the effect that low-speed and high-speed processing of programs can be performed appropriately and economically.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional memory control device. 1...Memory control device, 2...High speed ROM, 3...
・High-speed ROM control circuit, 4...Low-speed ROM, 5...Low-speed ROM control circuit, 6...Wait control circuit, 7...
・Processor.

Claims (1)

[Claims] a first fixed storage device containing a program that requires high-speed processing in real time; a first control means for controlling reading of the first fixed storage device; and a second fixed storage device containing a program for low-speed processing. a storage device, a second control means for controlling reading of the second fixed storage device, and the first and second control means for making the first and second fixed storage devices accessible from a processor. 1. A memory control device comprising: weight control means for generating weights and controlling transmission.