JPS6346762A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPS6346762A
JPS6346762A JP19123086A JP19123086A JPS6346762A JP S6346762 A JPS6346762 A JP S6346762A JP 19123086 A JP19123086 A JP 19123086A JP 19123086 A JP19123086 A JP 19123086A JP S6346762 A JPS6346762 A JP S6346762A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
elements
semiconductor device
side surfaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19123086A
Other languages
Japanese (ja)
Inventor
Hisao Hayashi
久雄 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP19123086A priority Critical patent/JPS6346762A/en
Publication of JPS6346762A publication Critical patent/JPS6346762A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain twice semiconductor elements from one transparent substrate by using the transparent substrate as an insulating substrate, observing a scribing region formed on one side surface through from the other side surface, and bringing it into coincidence with both side surfaces through the substrate to form semiconductor elements on both side surfaces of the substrate. CONSTITUTION:An insulating substrate is used as a transparent substrate 1, a scribing line 7 region formed on one side surface is observed through from the other side surface, and the scribing line 7 regions are brought into coincidence with both side surfaces through the substrate 1 to form semiconductor elements 6 on both side surfaces. That is, the line 7 is commonly formed to form the elements 65 on both front and rear surfaces of the substrate 1, and the elements 6 are executed for operation tests after a series of semiconductor processing steps are finished, and scribed to be divided, and only the elements of good products are used. Accordingly, most of the processing steps of the semiconductor, such as growing, annealing, oxidizing and etching of a polycrystalline Si by CVD can be simultaneously executed for both front and rear surfaces of the substrate 1. Thus, the number of the steps is not almost increased to obtain twice the elements 6 as large as the conventional case from one substrate 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に歩留り良く製造できる
大面積の半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a large-area semiconductor device that can be manufactured with high yield.

〔発明の概要〕[Summary of the invention]

本発明は、絶縁基板上に半導体層が形成され、その半導
体層に複数の半導体素子が形成されている半導体装置に
於いて、絶8!基板を透明基板とし、一方の面に形成し
たスクライブライン領域を他の面から透視し、前記スク
ライブ領域を両面で前記基板を介して一致させ、前記基
板両面に前記半導体素子を形成することによって、歩留
り良く製造される半導体装置を提供するものである。
The present invention provides a semiconductor device in which a semiconductor layer is formed on an insulating substrate and a plurality of semiconductor elements are formed in the semiconductor layer. The substrate is a transparent substrate, a scribe line area formed on one side is seen through from the other side, the scribe areas are aligned on both sides through the substrate, and the semiconductor element is formed on both sides of the substrate, It is an object of the present invention to provide a semiconductor device manufactured with high yield.

〔従来の技術〕[Conventional technology]

液晶デイスプレィデバイス、サーマルヘッド、イメージ
センサ−等のマン−マシン インターフェースの役割を
果たす半導体デバイスは、その1個のペレットの大きさ
が必然的に大きくなる。
Semiconductor devices that play the role of man-machine interfaces, such as liquid crystal display devices, thermal heads, and image sensors, inevitably have a large pellet size.

例えば2インチカラーテレビ液晶デイスプレィデバイス
には、3X4cmの領域に7万個ものトランジスタが作
り込まれている。これらの半導体素子は、5インチ又は
6インチの石英の片面にa−3iや多結晶Si層を設け
て、その中に数万個のトランジスタを作りつけることに
よって形成される。各絵素を構成する液晶に引加される
電圧を各トランジスタが、コントロールする事によって
TV画面が作られる。
For example, a 2-inch color television liquid crystal display device has as many as 70,000 transistors built into a 3 x 4 cm area. These semiconductor devices are formed by providing an A-3I or polycrystalline Si layer on one side of a 5-inch or 6-inch quartz and building tens of thousands of transistors therein. A TV screen is created by each transistor controlling the voltage applied to the liquid crystal forming each picture element.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

半導体装置の歩留りは、半立体素子1個当たりの専有面
積が小さければ小さくなる程、向上する。
The yield of semiconductor devices improves as the area occupied by one half-dimensional element becomes smaller.

マン−マシン インターフェース用の半導体素子はその
大きさが通常のDRAM等のICの数10倍もあるので
、例えマン−マシン インターフェース用の半導体素子
が非結晶材料により形成されていて、単結晶基板に形成
される半導体素子程良好な特性が必要とされないとして
も、その製造の歩替りを向上させる事は橿めて困難であ
る。例えば、カラーテレビ用液晶デイスプレィデバイス
の場合7万個もの素子のうちで、不良として許されるト
ランジスタの数は僅か5個である。と言うのは、トラン
ジスタの不良が発生すると、そのトランジスタのある画
素は動作しなくなり、変化する映像の中でその点のみが
白い点となり非常に見苦しい画面となる。しかしながら
現在の製造技術で、不良トランジスタを5個未満にする
事は不可能ではないが、それによるコスト高は極めて大
である。そこで両者の調整をとって現在の所2インチカ
ラーテレビ用液晶デイスプレィデバイスの場合、不良ト
ランジスタが5個以下の素子は良品とされている。
Semiconductor elements for man-machine interfaces are several tens of times larger than ICs such as ordinary DRAMs, so even if semiconductor elements for man-machine interfaces are made of amorphous materials, they cannot be fabricated on single-crystal substrates. Even if the characteristics of the semiconductor device to be formed are not as good as that of the semiconductor device being formed, it is extremely difficult to improve the manufacturing yield. For example, in the case of a color television liquid crystal display device, out of 70,000 elements, only 5 transistors are allowed as defective. This is because when a defective transistor occurs, the pixel in which the transistor is located stops working, and that point becomes the only white dot in the changing image, resulting in an extremely unsightly screen. However, although it is not impossible to reduce the number of defective transistors to less than five using current manufacturing technology, the cost increases accordingly. Therefore, adjustments have been made between the two, and currently, in the case of liquid crystal display devices for 2-inch color televisions, devices with 5 or fewer defective transistors are considered to be good products.

これらの素子は実際には、第2図に示すように、6イン
チの石英板1に6個(1個:3X4cm)形成される。
Actually, six of these elements (one piece: 3×4 cm) are formed on a 6-inch quartz plate 1, as shown in FIG.

しかし6個形成して6個全てが良品(不良トランジスタ
が5個以下)と言う事はなく、3儲程度の素子は不良品
となってしまう。この歩留りを向上させる事が製品価格
を下げる上で非常に重要なファクターとなっている。
However, even if six transistors are formed, all six transistors will not be good (with five or fewer defective transistors), and the elements with about three transistors will be defective. Improving this yield is a very important factor in lowering product prices.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明は、絶8(基板上に半導体層が形成し、その半導
体層に複数の半導体素子が形成されている半導体装置に
於いて、絶縁基板を透明基板とし、一方の面に形成した
スクライブライン領域を他の面から透視し、前記スクラ
イブ領域を両面で前記基板を介して一敗させ、前記基板
両面に前記半導体素子を形成することによって」二記問
題点を解決した。
The present invention relates to a semiconductor device in which a semiconductor layer is formed on a substrate and a plurality of semiconductor elements are formed on the semiconductor layer. The second problem was solved by viewing the area from another side, making the scribe area pass through the substrate on both sides, and forming the semiconductor element on both sides of the substrate.

〔作用〕[Effect]

本発明は、スクライブラインを共通させて透明基板の表
裏に半導体素子を形成し、一連の半導体処理工程が終了
してから、各半導体素子毎に動作テストを行い、スクラ
イブ分割して良品の半導体素子のみを使用するものであ
る。
In the present invention, semiconductor elements are formed on the front and back sides of a transparent substrate using a common scribe line, and after a series of semiconductor processing steps are completed, an operation test is performed on each semiconductor element, and the scribe is divided to determine whether the semiconductor element is good. It is used only.

CVDによる多結晶Siの成長、アニーリング、酸化、
エンチング等の半導体の処理工程の多くは、基板の表裏
両面に対して同時に行うことができる。
Growth of polycrystalline Si by CVD, annealing, oxidation,
Many semiconductor processing steps, such as etching, can be performed on both the front and back surfaces of a substrate at the same time.

従って、従来のように石英基板の片側しか使用していな
かった半導体装置に比較して、本発明の半導体装置によ
ると、殆ど工程数を増やすことなく一枚の基板から従来
の場合の倍の半導体素子を得ることができる。
Therefore, compared to a conventional semiconductor device that uses only one side of a quartz substrate, the semiconductor device of the present invention can produce twice as many semiconductors from a single substrate without increasing the number of steps. element can be obtained.

また、半導体工業に用いられる石英は両面にオプティカ
ルフラット加工がしであるのに、従来の様に石英板の片
側しか使用しないのは無駄な事であり、また両面を同時
に処理しても全体の処理工程数をそれ程増大させずに倍
の半導体素子が得られ、その結果基板1枚当たりの歩留
りが向上するとの認識に基づいて本発明がなされた。
In addition, although quartz used in the semiconductor industry has optical flat processing on both sides, it is wasteful to use only one side of the quartz plate as in the past, and even if both sides are processed at the same time, the overall The present invention was developed based on the recognition that twice the number of semiconductor devices can be obtained without significantly increasing the number of processing steps, and as a result, the yield per substrate can be improved.

スクライブ分割したペレットの表側の素子が良品で、裏
側の素子が不良品の場合、裏側の素子は無視して表側の
素子を所定位置にマウントする。
If the element on the front side of the scribe-divided pellet is good and the element on the back side is defective, the element on the back side is ignored and the element on the front side is mounted in a predetermined position.

各絵素は140μm口で、その中にトランジスタが占め
る面積は1χ程度なので、裏面のトランジスタの存在が
表側の素子に悪影♂を与えることはなくわざわざ裏面の
半導体素子を除去する必要はない。
Each picture element has a 140 μm opening, and the area occupied by the transistor therein is about 1χ, so the presence of the transistor on the back side does not have an adverse effect on the element on the front side, and there is no need to take the trouble to remove the semiconductor element on the back side.

〔実施例〕〔Example〕

第1図A〜Mによって、本発明の半導体装置をその製造
工程に基づいて説明する。これらの図面に於いて、各素
子、各層等の寸法は正しい比例関係の下に画かれていな
い。特にスクライブライン7の巾は20μmしかないが
、便宜上これらの図面に於いては各半導体素子は離して
画かれている。
The semiconductor device of the present invention will be explained based on its manufacturing process with reference to FIGS. 1A to 1M. In these drawings, the dimensions of elements, layers, etc. are not drawn to scale. In particular, the width of the scribe line 7 is only 20 μm, but for convenience, each semiconductor element is drawn separately in these drawings.

A 厚さ800μm、直径6インチの石英基板1の両面
に減圧気相成長法により多結晶5i62を成長させる。
A: Polycrystalline 5i62 is grown on both sides of a quartz substrate 1 with a thickness of 800 μm and a diameter of 6 inches by a low pressure vapor phase growth method.

B 片面にフォトレジスト層3を設けて、6個の半導体
素子を得るためのパターンニングを行う。
B. A photoresist layer 3 is provided on one side, and patterning is performed to obtain six semiconductor elements.

cg面にもフォトレジスト層3を設け、表側のバタンと
同じ位置にパターンを形成し、スクライブラインが表と
裏側で同じ位置に来るようにする。基板1が透明な石英
板であるので、表側と裏側のパターンの位置は容易に一
敗させる事ができる。
A photoresist layer 3 is also provided on the CG surface, and a pattern is formed at the same position as the front side batten so that the scribe line is at the same position on the front and back sides. Since the substrate 1 is a transparent quartz plate, the positions of the patterns on the front and back sides can be easily adjusted.

D 表・裏に設けたフォトレジストパターン3によって
、多結晶Si層2をエツチングする。
D Etch the polycrystalline Si layer 2 using photoresist patterns 3 provided on the front and back sides.

E ゲート酸化膜としてSiO□層4を減圧気相成長法
により表と裏に同時に形成する。
E. A SiO□ layer 4 is formed as a gate oxide film on the front and back sides simultaneously by low pressure vapor phase epitaxy.

F ゲート電)】となる多結晶5i5sを表と裏に同時
に形成する。
Polycrystalline 5i5s (F gate electrode) is formed simultaneously on the front and back sides.

以下の処理は、全て表側と裏側の面に対して同時に行わ
れる。
All of the following processes are performed simultaneously on the front and back sides.

G 多結晶Si層5をエツチングすることS二より各ト
ランジスタのゲート電極を形成する。
G. Etching the polycrystalline Si layer 5 S2 forms the gate electrode of each transistor.

11  多結晶Si層4に、多結晶Siゲート電極をマ
スクとして、イオン注入によりソース・ドレイン領域を
形成する。
11. Source/drain regions are formed in the polycrystalline Si layer 4 by ion implantation using the polycrystalline Si gate electrode as a mask.

I  SiO□膜を成長させる。I. Grow a SiO□ film.

J 配線電極用のコンタクトホールを5in2膜に形成
する。
J Form a contact hole for a wiring electrode in a 5in2 film.

K  Al金属をスパッタリングして配線電極を形成す
る。
Wiring electrodes are formed by sputtering K Al metal.

L プラズマCVD法によって5iJn膜をパンシヘー
ション膜として形成する。
L A 5iJn film is formed as a panshidion film by plasma CVD method.

M ボンディングバンドにコンタクトホールを形成し、
各半導体素子の動作テストを行って、不良半導体素子を
判別してからスクライブを行う。
M Form a contact hole in the bonding band,
After performing an operation test on each semiconductor element and identifying a defective semiconductor element, scribing is performed.

これらの製造方法により、3X4cm大の2インチカラ
ーテレビ用液晶駆動デバイスが6インチ石英基!Fi1
枚当たり12個得られる。例え歩留りが5割であっても
、1枚の石英基板から6個の良品半導体素子が得られる
By using these manufacturing methods, a 6-inch quartz-based liquid crystal drive device for a 2-inch color TV with a size of 3 x 4 cm can be produced! Fi1
You can get 12 pieces per sheet. Even if the yield is 50%, six good semiconductor devices can be obtained from one quartz substrate.

なお、この様にして両面にデバイスの形成されたペレッ
トを別のLSIチップ上にはり合わせ、下側のデバイス
を下地チップと接続し、上側のデバイスをワイヤボンデ
ィングすることによってマルチスタックチップを構成す
ることもできる。
Note that a multi-stack chip is constructed by gluing the pellet with devices formed on both sides in this manner onto another LSI chip, connecting the lower device to the base chip, and wire bonding the upper device. You can also do that.

〔発明の効果〕〔Effect of the invention〕

本発明の半導体装置により、従来の製造方法と殆ど工程
数を変えずに一枚の透明基板から2倍の半導体素子を得
ることができるので、結果として一枚の基板光たりの半
導体素子の歩留率を格段に向上させることができる。
With the semiconductor device of the present invention, twice as many semiconductor elements can be obtained from one transparent substrate with almost no change in the number of steps compared to conventional manufacturing methods, resulting in a reduction in the number of semiconductor elements per substrate. The retention rate can be significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A−Mは、本発明の半導体装置の製造工程を示す
。 第2図は基板上の半導体素子を示す。
1A to 1M show the manufacturing process of a semiconductor device of the present invention. FIG. 2 shows a semiconductor element on a substrate.

Claims (1)

【特許請求の範囲】[Claims]  絶縁基板上に半導体層を形成し、該半導体層に複数の
半導体素子を形成してなる半導体装置において、前記絶
縁基板として透明基板を用い、一方の面に形成したスク
ライブ領域を他方の面より透視し、前記スクライブ領域
を両面で前記基板を介して一致させ、前記基板両面に前
記半導体素子を形成したことを特徴とする半導体装置。
In a semiconductor device in which a semiconductor layer is formed on an insulating substrate and a plurality of semiconductor elements are formed on the semiconductor layer, a transparent substrate is used as the insulating substrate, and a scribe region formed on one surface is seen through from the other surface. A semiconductor device, wherein the scribe areas are aligned on both sides with the substrate interposed therebetween, and the semiconductor element is formed on both sides of the substrate.
JP19123086A 1986-08-15 1986-08-15 Semiconductor device Pending JPS6346762A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19123086A JPS6346762A (en) 1986-08-15 1986-08-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19123086A JPS6346762A (en) 1986-08-15 1986-08-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6346762A true JPS6346762A (en) 1988-02-27

Family

ID=16271063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19123086A Pending JPS6346762A (en) 1986-08-15 1986-08-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6346762A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5640308A (en) * 1991-06-14 1997-06-17 Aptix Corporation Field programmable circuit module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5640308A (en) * 1991-06-14 1997-06-17 Aptix Corporation Field programmable circuit module

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