JPS6346700A - Peak holding circuit - Google Patents

Abstract

PURPOSE:To eliminate diodes by using a dynamic comparator and a MOS transistor. CONSTITUTION:A dynamic comparator COM1 and the MOS transistors M1, M2 having one terminal connected to the input terminal of the comparator COM1 and the other terminal connected to the output terminal thereof are provided. The dynamic comparator COM1, when an input signal is smaller than a maximum value, outputs the output of a second level, disconnects the conduction of the MOS transistors M1, M2 connecting an input signal to capacitors C1, C2 until then, so that the voltage of the maximum value of the input signal is held in the capacitors C1, C2. Thereby, a peak holding circuit can be constituted without using diodes and a production is made easy and the reliability is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak hold circuit, and particularly to a peak hold circuit realized by a semiconductor integrated circuit.

[Conventional technology]

Conventionally, this type of peak hold circuit, as shown in Fig. 4, has the (E) input of the operational amplifier OP1 as the input terminal, the anode side of the diode DI is connected to the output, and the cand side is connected to one terminal of the capacitor tC1. and operational amplifier OP, (
Connected to the pull input. Further, the other terminal of the capacitor fC is grounded. Furthermore, the ←) input of the operational amplifier OP2 is connected to the output of this operational amplifier OP2, forming a so-called geltage follower, and this output is connected to the output terminal υ, which is further connected to the ←) input of the operational amplifier OP2. There is.

The input signal Min input to this circuit is the operational amplifier O
P, which is basically connected as a voltage follower with a gain of 1 and a positive phase output. However, in this case, diode D1 and capacitor C are included in the feedback loop.
It contains a half-wave rectifier circuit consisting of OP 1 and a voltage follower consisting of an operational amplifier OP2. So “,V
d is operational amplifier OP! The output voltage of capacitor C, Vp, is
The voltage across 1, VOUT is the output voltage of operational amplifier OP2 (!:, Vin=Vp=Voty,
Vd=Vp+ (forward droop voltage of diode D). In the case of this circuit, when Vin exceeds VOUT (changes in the +1 direction), the above-mentioned terminal voltages maintain the above relationship, but when Vin changes midway in the H direction, Vd decreases, Since there is a vprt diode D1, it remains unchanged, so VOUT also remains unchanged.

In this way, the input signal Vin (from -1-1 direction←
) direction, the voltage of Vp is transferred to capacitor C! to obtain the output voltage VOUT. Further, if the input signal Vin higher than Vp maintained by the capacitor tCt does not enter, Vprt is held at its value and vOUT is output.

[Problem that the invention seeks to solve]

However, the conventional peak hold circuit described above uses a diode, and when trying to implement this diode on a MOS integrated circuit, 1. Because it is impossible to create a diode that does not connect both the anode and cand to a fixed potential in the normal manufacturing process. There is a drawback that 9% cannot be accumulated all at once.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a peak hold circuit which does not require the use of the above-mentioned diodes by using a dynamic comparator and a MOS transistor.

[Failure to solve the problem]

In the present invention, bias periods and comparison periods are given alternately, and when an input level higher than the input level input in the previous bias period is input in the comparison period, a first level is output. , a dynamic comparator that holds and outputs a second level when an input level lower than the level input in the previous bias period is input; one terminal is connected to the input terminal of this comparator, and the other terminal is connected to the input terminal of this comparator. MOS transistor whose terminal is connected to the output terminal.

a capacitor provided between the output terminal and the earth;
Logic that applies an ON signal to the gate terminal of the MOS transistor at least during a comparison period while the comparator is outputting a first level, and applies an OFF signal when the comparator is outputting a second level; and a circuit.

With the above configuration, the dynamic comparator outputs the second level output when the input signal becomes smaller than the maximum value, cutting off the conduction of the MOS transistor that had connected the input signal to the capacitor up until this point. , the voltage of the maximum value of the input signal is held in the capacitor.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the first embodiment of the present invention.
, and the other terminal of this capacitor C is connected to ground. Also MOS transistor M and capacitor C! The connection point with is connected to the output terminal. Furthermore, the input terminal is a Guinabavuku type comparator COM,
A clock is connected to the comparator C0M1, and the output of the comparator C0M1 and the clock are respectively connected to the input of the NOR circuit NO.

The output of the f'JOB circuit NOR is connected to the gate terminal of the MOS transistor M1.

In addition, a dynamic type comparator COM, a capacitor CI connected in series between the 3-power terminal and the output terminal.
and inverter I! and latch circuit L! and connect the respective terminals to the input and output of this inverter Il, and
It is composed of a bias MOS transistor M2 to which a clock is connected to the gate terminal.

FIG. 2 is a waveform diagram at the main points in FIG. 1.

Hereinafter, the operation of FIG. 1 will be explained with reference to FIG. 2.
The 10° period is the comparison period, and the “1” period is the bias period. First, in the comparison period when the first clock signal φ is 101, the output V of the latch circuit L1. Ha, inverter! Since the output is H voltage, the time is 10 seconds. Therefore, the output of the NOR circuit NOR is φ/, t-tl. Therefore, MOS transistor M is in the ON state.

The input signal Vin applied to the input terminal causes Ct is charged. In the next bias period when the clock signal φ is 111, the MOS transistor M! is in the OFF state, comparator C0M1 is MOS transistor M
, is in the ON state.

If the input and output of the ino(-ta) 11 are both at the earth's potential,
A bias is applied to the capacitor C1, resulting in a bias state. At this time, the state 101 before the latch circuit Lte'i
is maintained. Next, the clock signal φ is again I □ I
In the comparison period, the input signal Vin applied to the capacitor C1 becomes the input signal V which was observed in the previous comparison period
If it is larger than the level of in, from inverter 11←
) [pressure is output, and if it is small, the inverter E1 outputs the (interest voltage). Then, from the inverter E!
When the pressure e is output, the latch circuit [, 1 outputs 111 and latches this state. This 11" output is NO
Turn off the MOS) run jisume M1 via the R circuit NOR.
State 1c (/, charging of the capacitor C3 by the input signal Vin is cut off, and the state of the capacitor C8 is maintained. Note that the level of the input signal Vin applied during the comparison period is the same as the level of the input signal applied during the previous comparison period. While the level of the signal Vin is low, the comparison period and bias period described above are repeated, and the maximum input signal Vin is accumulated on the capacitor C2.

FIG. 3 is a block diagram of a second embodiment of the invention.

The dynamic, two-way type comparator COM is the same as in FIG. 1 except that it uses an operational amplifier OP3, whereas the comparator COMB in FIG. 1 uses an inverter 11. In Fig. 3, the bias point is not set to a constant value in the case of using the inverter shown in Fig. 1, whereas the operational amplifier OP is used.

This takes advantage of the advantage that when using 1-, the common level can maintain a constant value as a bias point.

That is, if an analog C-channel MOS transistor is used as the MOS transistor M, the capacitor fC1 and MO
The connection point with the terminal of the S transistor M must always be at a level between the power supply and the ground, but if an inverter is used, the above connection point must be at a bias potential between the power supply or the ground. However, if an input with an excessive amplitude is applied during the first comparison period, the potential at the bias point may jump out from the power supply or the ground. In such a case, the drain diffusion layer of the P-channel MOS transistor or the N-channel MOS transistor is biased in the forward direction, and the charge in the capacitor C1 is discharged, causing malfunction. To prevent this, there is no other way than to limit the input amplitude when using an inverter, but when using a differential operational amplifier,
Since the bias point can be set anywhere, the upper limit of the amplitude of the input signal can be set to the maximum by setting the bias point to a level midway between the power supply and the earth.

Although both FIGS. 1 and 2 assume that the positive peak value of the input signal is held, it is clear that the negative peak value can also be held by changing the polarity of the comparator.

Furthermore, in both Figures 1 and 2, the output of the latch circuit L1 and the clock φ are applied to the MOS transistor M1 via the NO circuit, but the output of the latch circuit L1 is inverted. It may also be applied to the MOS transistor M1.

Furthermore, in order to hold an accurate peak value, the clock cycle may be made faster, but in reality, the clock frequency is determined in consideration of noise and the like.

〔Effect of the invention〕

As explained above, since the present invention can configure a peak hold circuit without using a diode, it can be easily implemented on an MO8 integrated circuit, and has the advantage of facilitating manufacturing and improving reliability. be.

[Brief explanation of drawings]

FIG. 1 shows the first embodiment of the present invention. I diagram. 2 is a waveform diagram at the main points in FIG. 1, FIG. 3 is a diagram of a second embodiment of the present invention, and FIG. 4 is a diagram of a conventional example. J,M,----MOST5,COM,,
COM. ...Dynamic comparator, work 1...
...Inverter p, C,,C,...Capacitor, Ll...U,Sub circuit, OP,,OP,,O
F, ... operational amplifier. D! ······diode. Certain / Figure χ 2 Bacteria

Claims (1)

[Claims] Bias periods and comparison periods are given alternately, and when an input level higher than the input level input in the previous bias period is input in the comparison period, the first level is output, and the input level is input in the previous bias period. A dynamic comparator that holds and outputs a second level when an input level lower than the input level is input, and one terminal is connected to the input terminal of this comparator and the other terminal is connected to the output terminal. ON signal at least during the comparison period during which the comparator outputs the first level to the connected MOS transistor, the capacitor provided between the output terminal and the earth, and the gate terminal of the MOS transistor. and a logic circuit that provides an OFF signal when the comparator is outputting a second level.