JPS62171222A - Clock signal drive circuit - Google Patents

Abstract

PURPOSE:To sufficiently operate a complementary MOS analog switch even when a power voltage difference is small by providing a delay circuit retarding a clock signal fed to an input terminal and a capacitor whose one terminal is impressed with the signal and whose other terminal is connected to an output terminal. CONSTITUTION:An input terminal of a driver 13 amplifying a clock signal phiin fed to an input terminal 11 inversely is connected to the input terminal 11. Then the output terminal of the driver 13 is connected to an output terminal 12. Further, an input terminal of the delay circuit 14 retarding the clock signal phiin by a prescribed time is connected to the said input terminal 11. The input terminal of the inverter 15 is connected to the output terminal of the delay circuit 14 and the capacitor 16 is connected between the output terminal of the inverter 15 and the output terminal 12 of the signal phiout. The series connecting point between the emitter of a transistor (TR) 21 and a drain of a TR 22 is connected to the output terminal 12 of the clock signal phiout.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complementary MO3 type integrated circuit, and particularly to a clock signal driving circuit that generates a clock signal used in a switched capacitor filter or a chopper type comparator.

[Technical background of the invention] FIG. 16 is a circuit diagram of an integrating circuit provided at the input stage of a well-known complementary MO8 type switched capacitor filter (hereinafter referred to as SCF), and FIG. 3 is a timing chart of clock signals used in this integrating circuit.

In FIG. 16, the clock signal φ1 is vDD<”i
” level), its inverted clock signal φ1 becomes Vas(
At the "O" level), an analog switch (transmission gate) 43 configured by connecting an N-channel MOS transistor 41 and a P-channel MOS transistor 42 in parallel becomes conductive, and the input analog voltage IN
is stored in the capacitor 44. Next, clock signal φ1
is inverted to Vss and the inverted clock signal φ1 is inverted to Voo, the analog switch 4 which has been conducting until now becomes
3 becomes non-conductive. Furthermore, the clock signal φ2 is Vo
o, when the inverted clock signal φ2 becomes Vss, N
Channel MOS transistor 45 and P channel MOS
Another analog switch 47 configured by connecting transistors 46 in parallel becomes conductive, and the input analog voltage IN stored in the capacitor 44 is supplied to the operational amplifier circuit 48 for integration. Since an integrating capacitor 49 is connected between the output end and the input end of the operational amplifier circuit 48, when a voltage is supplied, the operational amplifier circuit 48 integrates the voltage and outputs the voltage OUT. Output.

FIG. 18 shows the clock signal φ1 used in the SCF,
FIG. 2 is a circuit diagram of a conventional clock signal drive circuit that generates φ1, φ2, and φ2. That is, the two-phase clock signals φa and φb generated by the clock signal generation circuit 51 are inverted and amplified by inverters 52 and 53, respectively, and outputted as the inverted clock signals φ1 and φ2. Further, each of the inverted clock signals φ1 and φ2 is inverted and amplified by inverters 54 and 55 to generate the clock signal φ2.
1 and output as φ2. Here, these two-phase clock signals φ1 and φ2 do not overlap each other as shown in FIG. 17, and have gate widths of Voo and Vss, respectively. Note that VDD and Vss are power supply voltages, and in a normal integrated circuit, for example, VDO is set to +5■ and Vss is set to Ov, respectively.

[Problems with the Background Art] By the way, when the SCF is operated by supplying the clock signal generated by the conventional clock signal drive circuit, the potential difference between the power supply voltages Voo and Vss is about 5V as described above. There is no problem when the potential difference is smaller than 5μ, but a problem occurs when the potential difference becomes smaller than 5μ.

FIG. 19 shows a case where the potential difference between the power supply voltages Voo and Vss is set to 5V as described above, and the amplitude of the clock signal generated by the clock signal drive circuit of FIG. 18 is set to 5V. The analog input voltage IN at the SCF of
(V) and the conduction resistance R (KΩ) of the analog switch 43 or 47. FIG. Note that the value of the analog input voltage IN is based on Vss, and the potential difference between both ends of the analog switch is approximately Ov. As shown in FIG. 19, when the amplitude of the clock signal is set to 5cm, the conduction resistance value of the analog switch is set to a low value of 1 OKΩ or less over the entire input voltage range. For this reason, the SCF shown in FIG. 16 operates normally.

On the other hand, FIG. 20 shows when the potential difference between Voo and Vss is 3V and the amplitude of the clock signal is 3■.
17 is a characteristic curve diagram showing the relationship between the analog input voltage IN and the conduction resistance R (KΩ) of the analog switch in the SCF of FIG. 16. FIG. In this way, when the amplitude of the clock signal is set to 3V, the input voltage is 1.4V to 1.5V.
Near v, the conduction resistance of the analog switch becomes so high that the analog switch is virtually no longer conductive. That is, in the SCF of FIG. 16, when the analog input voltage IN is around 1.4V to 1.5V with respect to Vss, the input voltage cannot be integrated, and an error occurs in the integration operation. Therefore, SC using such an integrating circuit
If a filter is constructed using F, problems such as distortion in the output waveform will occur due to this error.

Moreover, such a problem can be solved by using complementary MO as shown in FIG.
A similar problem occurs in a switched capacitor (SC) type chopper comparator configured using 8-type analog switches 61 to 63, a capacitor 64, and an inverter 65. That is, when the analog switches 61 to 63 in the chopper-type comparator having such a configuration are controlled by the clock signal generated by the conventional clock signal drive circuit shown in FIG. 18, v
If the potential difference between DD and Vse is about 3V or less, the analog switch will not conduct when the input voltage is around 1.4 to 1.5, and will no longer function as a comparator.

In this way, when controlling the operation of an analog switch using a clock signal generated by a conventional clock signal drive circuit, there is a drawback that the analog switch will not operate properly if the potential difference between the power supply voltages is low. be. For this reason, the above-mentioned SCF or SC type chopper comparator cannot be used in devices that operate at low voltage, such as recent electronic watches and small electronic computers that use complementary MO8 type integrated circuits. However, the above SCF
are used in speech synthesis, speech recognition, telephone communications, etc., while SC type chopper comparators are widely used in A/D converters and the like. Therefore, these S
If a CF or SC type chopper comparator can be used in low-voltage driven electronic clocks and small electronic calculators, it will be possible to provide these clocks and calculations with significant additional functions.

[Object of the invention] This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide complementary M
It is an object of the present invention to provide a clock signal drive circuit which can sufficiently operate an OS type analog switch and thereby enable the use of an SCF or an SC type chopper type comparator in a low voltage driven device.

[Summary of the Invention] To achieve the above object, the present invention provides a clock signal connected in series between an input terminal and an output terminal of a clock signal, and a first power supply and a second power supply, and supplied to the input terminal. A drive circuit comprising first and second transistors of the same polarity to which an opposite phase signal of a clock signal to be applied and a clock signal are respectively applied to each control electrode, and a series connection point of both transistors is connected to the output terminal. A clock signal driving circuit is provided, which includes a delay circuit that delays a clock signal supplied to the input terminal, and a capacitor to which a signal is applied to one end and whose other end is connected to the output terminal. According to the clock signal drive circuit having such a configuration, the amplitude of the clock signal obtained at the output terminal can be made greater than the potential difference between the first power source and the second power source. For this reason, the first
Even if the potential difference between the power supply and the second power supply is made relatively low, the amplitude of the output clock signal will exceed this potential difference, and the entire circuit including this clock signal drive circuit can be operated at a low voltage! 71ff
can be done.

[Embodiments of the Invention] The present invention will be described in detail below with reference to the drawings. 1st
FIG. 1 is a block diagram showing the configuration of an embodiment of a clock signal driving circuit according to the present invention. 11 in Figure 1
1 is an input terminal for the clock signal φin, and 12 is an output terminal for the clock signal φout. The input terminal 11 is connected to the input terminal of a driver 13 that inverts and amplifies the clock signal φ10 supplied to the input terminal 11.

The output terminal of this driver 13 is connected to the output terminal 12. Further, the input terminal 11 is connected to the input terminal of a delay circuit 14 that delays the clock signal φin for a predetermined period of time. The output terminal of this delay circuit 14 is connected to the input terminal of an inverter 15, and the inverter 15
A capacitor 16 is connected between the output terminal of the signal φout and the output terminal 12 of the signal φout.

FIGS. 2 and 3 are circuit diagrams showing specific configurations of the driver 13 in the embodiment circuit shown in FIG. 1, respectively.

The driver in FIG. 2 connects the collector and emitter electrodes of an NPN bipolar transistor 21 and the source and drain electrodes of an N-channel transistor 22 between a high potential voltage vDD and a low potential power supply voltage Vss. The clock signal φin supplied to the input terminal 11 is applied to the base electrode of the transistor 21 via the inverter 23, and the clock signal φin supplied to the input terminal 11 is applied to the gate electrode of the transistor 22. φin is directly applied, and a series connection point between the emitter electrode of the transistor 21 and the drain electrode of the transistor 22 is connected to the output terminal 12 of the clock signal φout.

The driver shown in FIG. 3 uses an N-channel MOS transistor 24 in place of the bipolar transistor 21 in the circuit shown in FIG.

FIG. 4 is a circuit diagram showing a specific configuration of the delay circuit 14 in the embodiment circuit shown in FIG. 1. In FIG. This delay circuit has an even number of inverters 30 connected in series between an input end and an output end, and a capacitor 31 connected between the output end of each inverter 30 and Vss.

Therefore, the output signal of this delay circuit is in phase with the input signal.

Next, the operation of the circuit configured as described above will be explained using the timing chart shown in FIG. First, when the input clock signal φin is Voo ("1'level)", the output signal of the inverter 23 in the driver 13 shown in FIG. 2 or 3 is at Vss ("O" level). At this time, the transistor 21 in the circuit of FIG. 2 or the transistor 24 in the circuit of FIG. 3 becomes non-conductive, and the transistor 22 becomes conductive. Therefore, the output terminal 12 is the driver 1
The output clock signal φout becomes Vsa.

On the other hand, at this time, the output signal of the delay circuit 14 is VDD, and the output signal V15 of the inverter 15 inverts this signal.
is set to Vss.

Next, when the input clock signal φin decreases from Voo to Vsa, the transistor 21 or the third
Transistor 24 in the circuit shown in the figure becomes conductive, and transistor 2
2 becomes non-conductive. As a result, the output terminal 12 is charged via the transistor 21 or 24 in the driver 13, and the output clock signal φout becomes DD-ΔV.

Here, what corresponds to the above ΔV is the voltage between the base and emitter of the bipolar transistor 21 when the driver 13 shown in FIG. 2 is used, and the voltage between the base and emitter of the bipolar transistor 21 when the driver 13 shown in FIG. 3 is used. This becomes the threshold voltage.

On the other hand, immediately after the input clock signal φin drops to Vss, the output signal of the delay circuit 14 still remains Voo, and the output signal of the inverter 15 also remains Vss. After this, the output signals of the inverters 30 in the delay circuit shown in FIG. 4 are sequentially inverted, and the output signal of the R final stage becomes Vs
When the voltage is inverted to s, the output signal V15 of the inverter 15 in the circuit of FIG. 1 subsequently rises to Voo. signal V1
5, the signal φOUT at the output terminal 12 changes from Voo-Δ to 2Voo due to the coupling by the capacitor 16.
-ΔV.

Next, the input clock signal φin changes from Vss to Vo.

When the voltage rises to 1, the transistor 22 in the circuit of FIG. 2 and the circuit of FIG. 3 becomes conductive, and the transistor 21 in the circuit of FIG.
Alternatively, the transistor 24 in the circuit of FIG. 3 becomes non-conductive. Therefore, the output terminal 12 is discharged via the transistor 22 in the driver 13, and the output clock signal φOU
t becomes Vss again. Furthermore, after this, the output signal of the inverter 30 at the final stage in the delay circuit of FIG.
Since t has already become Vss, φout does not change in particular.

In this way, the clock signal drive circuit according to the above embodiment outputs 2Vno- from SS as the output clock signal φout.
A signal with an amplitude in the range ΔV is 1q. That is,
In the conventional circuit, only a clock signal having an amplitude in the range from Vss to Voo can be obtained, but in the above embodiment circuit, a clock signal having I5#IA which is approximately twice the power supply voltage can be obtained at t7. Therefore, if the clock signal obtained by this circuit is applied to the gate electrode on the N-channel MOS transistor side of the analog switch in FIG. 16 or FIG. 21, the conduction resistance of this transistor can be made sufficiently low. I can do it.

6 and 7, respectively, the embodiment circuit of FIG. 1 is replaced with the analog switch 43 or 47 in FIG.
FIG. 2 is a circuit diagram showing a specific configuration of the driver 13 used when the driver 13 is implemented to generate a clock signal to be applied to the gate electrode of the P-channel MOS transistor.

The driver in FIG. 6 connects a low-potential power supply voltage Vss and a high-potential power supply voltage Voo between the collector and emitter electrodes of a PNP type bipolar transistor 25 and between the source and train electrodes of a P-channel MOS l-transistor 26. The clock signal φin supplied to the input terminal 11 is applied to the base electrode of the transistor 25 via the inverter 27, and the clock signal φin is directly applied to the gate electrode of the transistor 26. The series connection point between the emitter electrode of the transistor 25 and the double voltage of the transistor 2G is connected to the clock signal φOU.
t output terminal] 2.

The driver shown in FIG. 7 uses a P-channel \IOS transistor 28 in place of the bipolar transistor 25 in the circuit shown in FIG. 6.

FIG. 8 is a timing chart showing the operation of the embodiment circuit of FIG. 1 when the driver 13 shown in FIG. 6 or 7 is used. Input clock signal φi
When n is Vss, the output signal of the inverter 27 in the driver of FIG. 6 or 7 is Voo. At this time, the transistor 25 or the seventh transistor in the circuit of FIG.
Transistor 28 in the illustrated circuit becomes non-conductive, transistor 261 . Pass through lta. Therefore, the output terminal 12 is charged via the transistor 26 in the driver 13, and the output clock signal φout becomes Voo. At this time, the output signal of the delay circuit 14 is Vss, and the output signal V15 of the inverter 15, which inverts this signal, is Voo.

Next, the input clock signal φin changes from Vss to Vo.

, transistor 25 in the circuit of FIG. 6 or transistors 1 to 28 in the circuit of FIG. 7 become conductive, and transistor 26 becomes non-conductive. As a result, the output terminal 12 is discharged via the transistor 25 or 28 in the driver 13. At this time, the output clock signal φout is V
It becomes ss+ΔV. However, Δ■ is the voltage between the base and emitter of the transistor 25 or the threshold voltage of the transistor 28.

On the other hand, immediately after the input clock signal φ1n rises to VDD, the output signal of the delay circuit 14 still remains at Vss, and the output signal of the inverter 15 also remains at Voo. Therefore, the capacitor 16 is charged with a voltage of Voo-Δ■.

After this, the inverter 30 in the delay circuit shown in FIG.
When the output signals of the inverter 30 at the final stage are inverted to Vss, the output signal V15 of the inverter 15 in the circuit of FIG. 1 subsequently decreases to Vss. Due to the decrease in the fi signal V15, the signal φout at the output terminal 12 becomes Vs due to capacitive coupling by the capacitor 16.
The voltage decreases by Vss-Voo from s+ΔV. In other words, the signal φOUT becomes -VDD+8V.

Next, when the input clock signal φin decreases from VDD to Vss, the transistor 2 in the circuit of FIG. 6 and the circuit of FIG.
6 becomes conductive, and transistor 25 in the circuit of FIG. 6 or transistor 28 in the circuit of FIG. 7 becomes non-conductive. Therefore, the output terminal 12 is connected to the transistor 2 in the driver 13.
6, and the output clock signal φou
t becomes Voo again. Furthermore, after this, the output signal of the inverter 30 at the final stage in the delay circuit of FIG.
Since t is already vDD, there is no particular change in φout.

In this way, the driver 13 as shown in FIG. 6 or 7
, the clock signal drive circuit of the above embodiment outputs a clock signal φOUT from VOO to −VDD+.
A signal with an amplitude in the range ΔV is obtained. That is, in the conventional circuit, only a clock signal whose lowest level is Vss is obtained, but in the above embodiment circuit, it is possible to obtain a clock signal having a level inversely negative to the voltage Voo. Therefore, if the clock signal generated by this circuit is applied to the gate electrode on the P-channel MOS transistor side of the analog switch in FIG. 16 or FIG. 21, the conduction resistance of this transistor can be made sufficiently low. can.

9 and 10 respectively show the analog input voltage IN (V) when the clock signal obtained by the clock signal drive circuit of the above embodiment is applied to the analog switch 43 in the circuit of FIG. 3 is a characteristic curve diagram showing the relationship between the analog switch 43 and the conduction resistance R (KΩ). FIG. Note that Voo is set to +3 and Vss is set to O■.

The characteristic curve diagram in FIG. 9 is obtained when a clock signal with increased amplitude is applied to both the N-channel and P-channel MOS transistors of the analog switch 43.

In this case, the value of conduction resistance is significantly lower than that in Figure 20 above, and the peak of conduction resistance that conventionally occurred around the input voltage of 1.4V to 1.5V also occurs. do not.

The characteristic curve diagram in FIG. 10 shows that the voltage generated by the conventional circuit is
This is a case where a clock signal having an amplitude between DD and Vss is applied, and a clock signal generated by the above embodiment circuit and having a large amplitude is applied only to the N-channel MOS transistor side. In this case Voo
If the potential difference between Vss and Vss is about 3V, the conduction resistance will be sufficiently low. Further, even if a clock signal generated by this embodiment circuit and having a large amplitude is applied only to the P-channel MOS transistor side, the conduction resistance can be made to be approximately the same as this 10th [Z].

Note that the slope of the characteristic curve in this case is negative, that is, the value of the conduction resistance is greatest in a region where the analog input voltage IN (V) is low.

The characteristic curve diagram in FIG. 11 shows that the analog switch 43 is composed of only one N-channel MOS transistor, and the clock signal obtained by the above embodiment circuit and having a large amplitude is applied to the gate electrode of this transistor. This is what happens when you do this.

In this case as well, if the potential difference between VDD and Vss is about 3V, the conduction resistance will be sufficiently lower than in the case of FIG. 20.

FIG. 12 is a circuit diagram showing the configuration of another embodiment of the invention. In the embodiment circuit shown in FIG. 1 above, a delay circuit 14 is used in which the phase of the signal obtained at its output terminal and the input signal are equal; however, in this embodiment, the output signal and the input signal are A delay circuit 17 having an opposite phase is used. Such a delay circuit 17 is
Inverters 30 connected in cascade in the circuit of FIG.
This is achieved by making the number of . Further, as an input signal to this delay circuit 17, an input clock signal φ
The output signal of the inverter 23 in the driver 13 from which an inverted signal of in is obtained is applied.

FIG. 13 is a block diagram showing the configuration of an applied example of the present invention. This application example circuit is constructed by providing a plurality of clock signal drive circuits of the embodiment shown in FIG. 1 and connecting them in multiple stages. Note that for multi-stage connection, a subsequent-stage driver 13 having a signal inversion function is used in place of the inverter 15 provided in each clock signal drive circuit configured as shown in FIG. That is, input terminal 1
1 is connected to the input terminals of the first-stage driver 131 and the first-stage delay circuit 141. The output terminal of the driver 131 is connected to the output terminal 12, and the delay circuit 141
The input terminal of a next-stage driver 132 used in place of the inverter 15 is connected to the output terminal of the inverter 15 . Furthermore, a capacitor 161 is connected between the output end of this driver 132 and the output terminal 12.

The output terminal of the delay circuit 141 is further connected to the input terminal of a delay circuit 142 of the next stage clock signal drive circuit. The output terminal of this delay circuit 142 is connected to the inverter 1.
The input terminal of the next-stage driver 13, which is used in place of driver 5, is connected thereto. Furthermore, a capacitor 1 is connected between the output terminal of this driver 133 and the output terminal of the driver 132.
62 are connected.

Thereafter, a plurality of clock signal drive circuits are connected in multiple stages in the same manner, and in the Nth clock signal drive circuit, which is the final V, the input terminal of the delay circuit 14N is connected to the output terminal of the delay circuit 14 in the previous stage. An input terminal of a driver 13N+1 serving as an inverter is connected to an output terminal of the delay circuit 14N. Roughly speaking, a capacitor 16N is connected between the output terminal of this driver 13N+1 and the output terminal of the driver 13 at the preceding stage. Here, each of the N+1 drivers 13 except for the final stage has the same configuration as, for example, one of the above-mentioned FIGS. 2, 3, 6, and 7, and the final stage is The inverter may be configured similarly to these or may be a simple inverter.

In other words, such a lock signal drive circuit has a delay circuit 14N of the Nth stage clock signal drive circuit which is the final stage.
The point to which the output terminal of the driver 13N+1 is connected is the first circuit point 18, and the point to which the output terminal of the driver 13N+1 is connected is the second circuit point 19. N delay circuits 141 to 14N are connected in series to
N capacitors 161 to 16N are connected in series between the output terminal 12 and the second circuit point 19, and the input terminal 11
Connect the driver 131 between the output terminal 12 and N-
N- between each output terminal of one delay circuit 141 to 14N- and the series connection point of the first and (I+1>(I=1 to N-1) capacitors 161 and 16N-1)
The drivers 132 to 13N-1 of IIIiI are connected to each other, and the driver 13N+1 is connected between the first circuit point 18 and the second circuit point 19.

FIG. 14 is a timing chart showing the operation of the applied example circuit of FIG. 13 above. However, in this case driver 1
Assume that the device shown in FIG. 2 is used as the device 3. First, when the input clock signal φ1n is at VDD, the output signals of all delay circuits 14 are also at VDD. Therefore, the output signals of the inverters 23 in all the drivers 13 are at Vss, the transistors 21 are non-conductive, and the j-transistors 22 are conductive. Therefore, the signal φout at the output terminal 12, the signal V at each series connection point of the capacitor 16 and the second circuit point 19
1 to VN all become Vss.

Next, when the input clock signal φin decreases to Vsa, first the transistor 21 in the driver 131 becomes conductive and the transistor 22 becomes non-conductive. This allows output terminal 1
Similarly to the above, the signal φout of No. 2 rises to VDD-ΔV. Subsequently, the output signal of the delay circuit 141 becomes Vssl:, the transistor 21 in the driver 132 becomes conductive, and the transistor 22 becomes non-conductive.

As a result, the output signal V1 of this driver 132 becomes VDD.
-ΔV. Further, due to the capacitive coupling of the capacitor 161, the signal φout becomes VDD−
ΔV increases by VD+)−ΔV. Therefore, the signal φo
ut increases to 2 (Voo-ΔV). Subsequently, the output signal of the delay circuit 142 becomes Vss, the transistor 21 in the driver 133 becomes conductive, and the transistor 22 becomes non-conductive. As a result, the output signal V of this driver 133
2 rises to VDD-ΔV. Also, as the signal V2 rises, due to the capacity f1 of the cabling 162, 2
The signal φout that has risen to DD−ΔV) becomes Vo o −
ΔV bamboo rise LT3 (Vo o −ΔV) 1. :
Become.

Thereafter, similar operations are performed sequentially to cause i! of the R91st stage. ! The output @ of the extension circuit 14N becomes Vss, the transistors 21 in the drivers 13 to +1 become conductive, and the transistors 22 become non-conductive. This will cause this driver 1
The output signal VN of 3N+1 rises to Voo-ΔV, and due to the capacitive coupling of the capacitor 16N, the output clock signal φo
ut increases to N(VaD-ΔV).

In this way, in this application example circuit, input clock signals φ1n to V9g and N having amplitudes only between Vss and Voo are
Clock signal φo with an amplitude between (Voo - ΔV)
ut can be generated. Therefore, if the clock signal generated by this circuit is used to control the N-channel MOS transistor of the analog switch, this Mo8I
- The conduction resistance of the transistor can be made sufficiently low.

Roughly speaking, in this applied example circuit, if the driver 13 is configured as shown in FIG. 6 or 7, it is possible to generate a clock signal having a negative polarity level as described above. If the generated clock signal is used to control the P-channel MOS transistor of the analog switch, the conduction resistance of this MOS transistor can be made sufficiently low.

FIG. 15 is a block diagram showing the configuration of another application example of the present invention. This application example circuit replaces each delay circuit 14 in the application example circuit of FIG.
As in the case of the twenty-eighth embodiment, a delay circuit 17 having a signal inversion function is provided. Therefore, the input terminal of each delay circuit 17 is connected to the inverter 23 in the driver 13.
(However, the driver 13 is configured as shown in FIG. 2 or 3). Also in this case, the final stage driver 13N+1 may be configured in the same manner as in FIGS. 2, 3, 6, and 7, or may be a simple inverter.

By the way, in the above two named embodiments and each application example circuit,
The reason why the driver 13 is composed of two transistors of the same polarity and an inverter as shown in FIGS. 2, 3, and 1M7 is as follows. That is, the output terminal of the driver 13, for example, in the case of FIG. 2, the connection point between the emitter N pole of the bipolar transistor 21 and the drain electrode of the MOS transistor 22 is supplied to the collector electrode of the i-transistor 21. An even higher voltage than the power supply voltage VDD can be obtained. However, the high voltage 1q applied to the output terminal of the driver 13 does not flow into the power supply Voo because the connection between the cap and the base voltage (of the transistors 1 to 21) is reverse biased by the PN junction. Ending, Driver 1
The high voltage obtained at the output terminal of 3 is maintained without any voltage drop. Further, in the case of the driver shown in FIG. 3, which uses an N-channel Mo8 l-transistor 24 instead of the bipolar transistor 21,
The power supply voltage V supplied to the source electrode of this MOS transistor 24 and the train 1 of this transistor 24
The voltage made higher than DD is (1).However, the semiconductor region of the N-channel MOS transistor connected to the source 1 is an N-type region, and this N-type region is formed in a P-type substrate or a P-type well region. between this N-type region and the P-type substrate or P-type well region.
Since it is reverse biased by the N junction, the high voltage obtained at the output of the driver 13 does not flow into the power supply Voo.

In this manner, each of the embodiment circuits and application example circuits described above can generate a clock signal having an amplitude larger than the amplitude between the voltages Vss and VDD. For this reason,
When controlling the operation of the analog switch using this clock signal, it is possible to operate the analog switch normally even if the potential difference between the voltage vA voltage is lowered. For this reason, it is now possible to use SCF and SC type chopper comparators in devices that operate at low voltages, such as electronic clocks that use complementary MO8 type integrated circuits and electronic compact calculators. Speech synthesis, 8-voice recognition, telephone communication, A/D converters, etc. can be used in low-voltage driven electronic clocks, electronic compact calculation sources, etc.

[Effects of the Invention] As explained above, according to the present invention, electric 2I! We have created a clock signal drive circuit that can sufficiently operate complementary MOS type analog switches even when the voltage potential difference is small, making it possible to use SCFs and SC chopper type comparators in low-voltage driven equipment. can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the clock signal driving circuit according to the present invention, and FIGS. 2 and 3 respectively show the specific configuration of some circuits in the embodiment circuit of FIG. FIG. 4 is a circuit diagram showing the specific configuration of some other circuits in the embodiment circuit shown in FIG. 1, FIG. 5 is a timing chart showing the operation of the embodiment circuit, and FIG. and FIG. 7 are circuit diagrams showing other specific configurations in place of the circuits in FIG. 2 and the third factor circuit, respectively, and FIG. 8 is an implementation of FIG. 1 using the circuit in FIG. 9 to 11 are characteristic curve diagrams for explaining the circuit of the above embodiment, and FIG. 12 is a circuit diagram showing the configuration of another embodiment of the present invention. FIG. 13 is a block diagram showing the configuration of an applied example of this invention, FIG. 14 is a timing chart of the above applied example circuit, FIG. 15 is a block diagram showing the configuration of another applied example of this invention, and FIG. 16 is an SCF 17 is a circuit diagram of an integrating circuit provided in the input stage of the integrator, and FIG. 17 is a timing chart of a clock signal used to control the operation of this integrating circuit.
The figure is a circuit diagram of a conventional clock signal drive circuit that generates the above clock signal, and FIGS. 19 and 20 are characteristic curves when controlling the operation of the integrating circuit shown in FIG. 17 using the above conventional circuit, respectively. Figure 21 is a circuit diagram of a switched capacitor type chopper comparator. 11...Input terminal, 12...Output terminal, 13...
Driver, 14... Delay circuit, 15... Inverter, 16... Capacitor, 17... Delay circuit, 18...
...First circuit point, 19...Second circuit point (2) 1.
・NPN type bipolar transistor, 22...N
Channel MOS transistor (2) 3... Inverter (2) 4... N channel MOS transistor,
25...PNP type bipolar transistor (2) 6
... P-channel MOS transistor (2) 7...
Inverter, 28... P channel MOS transistor, 3o... Inverter, 31... Capacitor. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Voo Vo. Fig. 6 Fig. 7 Fig. 9 Fig. 10 Fig. 11 Fig. 12 Fig. 13 Fig. 16 Fig. 17) Fig. 18 - IN(V) -INm Fig. 19 Fig. 20 Fig. 21

Claims (6)

[Claims] (1) A clock signal input terminal and an output terminal are connected in series between a first power source and a second power source, and a reverse phase signal of the clock signal supplied to the input terminal and a clock signal are connected to each control electrode. the first and second of the same polarity applied to
a drive circuit consisting of transistors, in which the series connection point of both transistors is connected to the above output terminal; and a delay circuit that delays the clock signal supplied to the above input terminal; A clock signal drive circuit comprising a capacitor connected to a terminal. (2) First to Nth delay circuits connected in series between the input terminal and output terminal of the clock signal, and the input terminal and the first circuit point, and sequentially delaying the clock signal supplied to the input terminal. and first to Nth capacitors connected in series between the output terminal and the second circuit point, and connected in series between the first power source and the second power source and supplied to the input terminal. A first signal of the same polarity that is applied to each control electrode, and a reverse phase signal of the clock signal to be applied to each control electrode.
, a first drive circuit configured with a second transistor, the series connection point of both transistors being connected to the output terminal, and the first drive circuit connected in series between the first power source and the second power source, and the (I=1 to N-1) of the output signal of the delay circuit and the third and fourth transistors of the same polarity are respectively applied to each control electrode, and the output signal of the delay circuit is The series connection points are the above I and (I+
1) second to (N-1)th drive circuits connected to the series connection points of the capacitors, and a second drive circuit that inverts and amplifies the signal at the first circuit point and supplies it to the second circuit point. A clock signal drive circuit comprising: N drive circuits. (3) The clock signal drive circuit according to claim 1, wherein the first transistor is a bipolar transistor, and the second transistor is a MOS transistor. (4) Both the first and second transistors are MOS
The clock signal drive circuit according to claim 1, which is comprised of transistors. (5) The first and third transistors are bipolar transistors, and the second and fourth transistors are MO
3. The clock signal drive circuit according to claim 2, each comprising an S transistor. (6) All of the first to fourth transistors are MOS
The clock signal drive circuit according to claim 2, which is composed of transistors.