JPH0323659A - Substrate potential setting circuit - Google Patents

Substrate potential setting circuit

Info

Publication number
JPH0323659A
JPH0323659A JP1158525A JP15852589A JPH0323659A JP H0323659 A JPH0323659 A JP H0323659A JP 1158525 A JP1158525 A JP 1158525A JP 15852589 A JP15852589 A JP 15852589A JP H0323659 A JPH0323659 A JP H0323659A
Authority
JP
Japan
Prior art keywords
substrate potential
substrate
potential
oscillation
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1158525A
Other languages
Japanese (ja)
Other versions
JP2841480B2 (en
Inventor
Hiroyuki Goto
五藤 浩幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1158525A priority Critical patent/JP2841480B2/en
Publication of JPH0323659A publication Critical patent/JPH0323659A/en
Application granted granted Critical
Publication of JP2841480B2 publication Critical patent/JP2841480B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To keep a substrate potential definite by providing the following: a substrate- potential detection part; an oscillation part whose oscillation frequency is controlled according to the substrate potential; and a substrate-potential generation pumping circuit. CONSTITUTION:When a substrate potential Vsub is changed, a substrate-potential detection part 10 detects this change and gives a signal Vc1 according to the substrate potential to an oscillation part 20. The oscillation part 20 cescades inverters 21 to 23 and feeds back an output to the inverter 21. When the Vc1 is at 'H', the oscillation part is oscillated in a short cycle; when the Vc1 is at 'L', it is oscillated in a long cycle. A waveform of the oscillation part 20 is reshaped by using a waveform-reshaping part 30 which has cascaded inverters 31 to 34. A substrate-potential generation pumping circuit 40 executes a pumping operation according to an output of the waveform- reshaping circuit 30 by using a coupling capacity 43 which has been inserted between series-connected diodes 41, 42 and their connection point and the waveform-reshaping part 30; the substrate potential Vsub is lowered to a threshold value or lower of the Vsub. When it is lower than the threshold value, the oscillation part 20 is oscillated in the long cycle; the pumping circuit 40 maintains the substrate potential Vsub in a present state. By this constitution, the Vsub can always be definite.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体集積回路に内蔵されて基板電位を所定
の電位に設定する基板電位設定回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a substrate potential setting circuit that is built into a semiconductor integrated circuit and sets a substrate potential to a predetermined potential.

[従来の技術] ダイナミックRAM及び一部のスタティックRAM等の
半導体装置では、ポンピング動作によって基板電位(P
型基板の場合にはPサブ、N型基板の場合にはNウェル
)を接地電位よりも低いある一定の電圧に設定する基板
電位発生回路を内蔵している。
[Prior Art] In semiconductor devices such as dynamic RAM and some static RAM, the substrate potential (P
It has a built-in substrate potential generation circuit that sets the P sub in the case of a type substrate and the N well in the case of an N type substrate to a certain voltage lower than the ground potential.

第5図は、従来のこの種の基板電位発生回路を示す図で
ある。即ち、チップ選択信号CSが基板電位設定制御部
60に入力されると、3段のインバータEll,82.
83を介してこの信号CSがレベル変換され、基板電位
設定制御信号として発振部20に与えられる。発振部2
0では、基板電位設定制御信号が入力されると、インバ
ータ21,22.23が動作可能な状態になり、インバ
ータ23の出力をインバータ21の入力に帰還させるこ
とによって、これらインバータ21乃至23の信号伝達
時間に対応した周期の発振信号を出力する。この信号は
4段のインバータ31.32.38.34からなる波形
整形部30で波形整形され、基板電位発生ポンプ回路部
40に入力される。この基板電位発生ポンプ回路部40
は、基板と接地との間に、基板側をアノード、接地側を
カソードとして直列に接続されたダイオード41.42
と、これらダイオード41.42の接続点Aと波形整形
部30の出力部との間に接続された結合キャパシタ43
とによって構成され、波形整形部30から出力される発
振出力によって接続点Aの電位を振動させ、基板の電荷
を接地側に引き抜くように動作する。これにより基板電
位V tubを所定の電位まで引き下げることができる
FIG. 5 is a diagram showing a conventional substrate potential generation circuit of this type. That is, when the chip selection signal CS is input to the substrate potential setting control section 60, the three stages of inverters Ell, 82 .
This signal CS is level-converted via 83 and is applied to the oscillation section 20 as a substrate potential setting control signal. Oscillator 2
0, when the substrate potential setting control signal is input, the inverters 21, 22, and 23 become operational, and by feeding back the output of the inverter 23 to the input of the inverter 21, the signals of these inverters 21 to 23 are Outputs an oscillation signal with a period corresponding to the transmission time. This signal is waveform-shaped by a waveform shaping section 30 consisting of four stages of inverters 31, 32, 38, and 34, and is input to a substrate potential generation pump circuit section 40. This substrate potential generation pump circuit section 40
are diodes 41 and 42 connected in series between the substrate and ground, with the substrate side as the anode and the ground side as the cathode.
and a coupling capacitor 43 connected between the connection point A of these diodes 41 and 42 and the output part of the waveform shaping section 30.
It operates so as to oscillate the potential at the connection point A by the oscillation output output from the waveform shaping section 30 and draw out the charge on the board to the ground side. This allows the substrate potential V tub to be lowered to a predetermined potential.

[発明が解決しようとする課題コ しかしながら、上述した従来の基板電位設定回路におい
ては、チップ選択信号等の制御信号によって回路の動作
状態を制御し、基板電位を得るようにしているため、基
板電位は上記制御信号に依存することになる。このため
、何らかの理由によって基板電位が変動した場合、制御
信号の入力を待たなければ安定した基板電位が保障され
ないという問題点があった。
[Problems to be Solved by the Invention] However, in the conventional substrate potential setting circuit described above, the operating state of the circuit is controlled by a control signal such as a chip selection signal to obtain the substrate potential. will depend on the above control signal. Therefore, if the substrate potential fluctuates for some reason, there is a problem that a stable substrate potential cannot be guaranteed unless a control signal is input.

本発明はかかる問題点に鑑みてなされたものであって、
基板電位を常に安定した電位に維持させることができる
基板電位設定回路を提供することを目的とする。
The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a substrate potential setting circuit that can always maintain a stable substrate potential.

[課題を解決するための手段コ 本発明に係る基板電位設定回路は、半導体集積回路W!
置の基板電位を検出し基板電位に応じた信号を出力する
基板電位検知部と、この基板電位検知部から出力される
上記基板電位に応じた信号によって発振周波数が制御さ
れる発振部と、この発振部からの出力に応じて基板の電
荷を引き抜く基板電位発生ポンプ回路部とを具備してな
ることを特徴とする。
[Means for Solving the Problems] The substrate potential setting circuit according to the present invention is a semiconductor integrated circuit W!
a substrate potential detection section that detects the substrate potential of the substrate and outputs a signal corresponding to the substrate potential; an oscillation section whose oscillation frequency is controlled by a signal corresponding to the substrate potential output from the substrate potential detection section; The present invention is characterized in that it includes a substrate potential generation pump circuit section that extracts charges from the substrate according to the output from the oscillation section.

[作用コ 本発明においては、基板電位が変動すると、基板電位検
知部がこの変動を検知し、基板電位に応じた信号を発振
部に出力する。発振部は、上記信号に応じて発振周波数
を変化させる。これにより、基板電位発生ポンプ回路の
電荷引抜き能力が制御され、基板電位が常に一定の電位
となるように制御されることになる。このため、本発明
によれば、基板電位を常に一定の電位に保つことができ
る。
[Operations] In the present invention, when the substrate potential fluctuates, the substrate potential detection section detects this fluctuation and outputs a signal corresponding to the substrate potential to the oscillation section. The oscillation section changes the oscillation frequency according to the signal. As a result, the charge extraction ability of the substrate potential generation pump circuit is controlled so that the substrate potential is always kept at a constant potential. Therefore, according to the present invention, the substrate potential can always be kept at a constant potential.

[実施例] 以下、添付の図面に基づいて本発明の実施例について説
明する。
[Example] Hereinafter, an example of the present invention will be described based on the accompanying drawings.

第1図は本発明の第1の実施例に係る基板電位設定回路
を示す図である。
FIG. 1 is a diagram showing a substrate potential setting circuit according to a first embodiment of the present invention.

即ち、この基板電位発生回路は、基板電位を検出して基
板電位に応じた信号VOIを出力する基板電位検知部1
0と、この基板電位検知部10の出力信号VOIに基づ
いてその発振周波数が制御される発振部20と、この発
振部20からの発振出力を波形整形する波形整形部30
と、波形整形された発振出力に応動して基板電位を所定
の電位まで引き下げる基板電位発生ポンプ回路部40と
によって構成されている。
That is, this substrate potential generation circuit includes a substrate potential detection section 1 that detects a substrate potential and outputs a signal VOI according to the substrate potential.
0, an oscillation section 20 whose oscillation frequency is controlled based on the output signal VOI of the substrate potential detection section 10, and a waveform shaping section 30 that shapes the waveform of the oscillation output from this oscillation section 20.
and a substrate potential generation pump circuit section 40 that lowers the substrate potential to a predetermined potential in response to the waveform-shaped oscillation output.

基板電位検知部10は、基準電圧端子と接地端子との間
に直列に接続された抵抗11及びPチャネル型MOS}
ランジスタ12と、これらの接続点Bの電位を増幅する
増幅器13とによって構成されている。MOS}ランジ
スタ12のゲート電極には基板電位V sumが入力さ
れており、この基板電位V m.bによってソース●ド
レイン間の抵抗値が変化し、固定抵抗11との間の抵抗
分割によって接続点Bの電位が基準電位V r a f
から接地電位の間を変化する。なお、基準電位V r 
a tとしては、例えば3〜5v程度の任意の定電圧が
与えられる。接続点Bの電位は増幅器13によって増幅
され、接地電位〜電源電位のフルスイングの信号VCt
として出力される。この基板電位検知部10は、例えば
第2図に示すよろなDC伝達特性を持つように設計され
る。即ち、基板電位V subが所定のスレッシロルド
電位V @sob−thよりも高くなると、出力Vc1
はハイレベルとなり、同じくスレッシ1ルド電位V.。
The substrate potential detection unit 10 includes a resistor 11 and a P-channel MOS connected in series between a reference voltage terminal and a ground terminal.
It is composed of a transistor 12 and an amplifier 13 that amplifies the potential of these connection points B. A substrate potential V sum is input to the gate electrode of the transistor 12, and this substrate potential V m. b changes the resistance value between the source and drain, and the potential at the connection point B changes to the reference potential V r a f by resistance division with the fixed resistor 11.
Varies between ground potential and ground potential. Note that the reference potential V r
As at, for example, an arbitrary constant voltage of about 3 to 5 V is applied. The potential at the connection point B is amplified by the amplifier 13, and a full swing signal VCt from the ground potential to the power supply potential is generated.
is output as This substrate potential detection section 10 is designed to have various DC transfer characteristics as shown in FIG. 2, for example. That is, when the substrate potential Vsub becomes higher than the predetermined threshold potential V@sob-th, the output Vc1
becomes high level, and the threshold potential V. .

−。よりも低くなると、出力Vatはローレベルとなる
−. When the value becomes lower than , the output Vat becomes a low level.

発振部20は、制御端子付きのインパータ21,22.
23を縦続接続すると共に、インバータ23の出力をイ
ンバータ21の入力に帰還接続して構成されている。こ
の発振部20は、基板電位検知部10の出力信号VOI
のレベルによって、その発振周期を変化させる。即ち、
出力VOsがハイレベルのときには短い周期で発振し、
出力Vatがローレベルのときには長い周期で発振する
The oscillation unit 20 includes inverters 21, 22 .
23 are connected in cascade, and the output of the inverter 23 is feedback-connected to the input of the inverter 21. This oscillator 20 outputs the output signal VOI of the substrate potential detector 10.
The oscillation period changes depending on the level. That is,
When the output VOs is at a high level, it oscillates in a short period,
When the output Vat is at a low level, it oscillates with a long period.

波形整形部30は、4つのインバータ31,32,33
.34を縦続接続して構成され、上記発振部20からの
出力を波形整形する。
The waveform shaping section 30 includes four inverters 31, 32, 33.
.. 34 connected in cascade, and shapes the waveform of the output from the oscillation section 20.

また、基板電位発生ポンプ回路部40は、基板と接地端
子との間に、基板側をアノード、接地側をカンードとし
て直列に接続された例えばMOSトランジスタからなる
ダイオード41.42と、これらダイオード41.42
の接続点Aと波形整形部30の出力部との間に介挿され
た結合キャパシタ43とにより構成され、波形整形部3
0の出力に応じてポンピング動作を行い、基板電位V 
subを引き下げる働きを有する。
The substrate potential generation pump circuit section 40 also includes diodes 41 and 42, each of which is made of, for example, a MOS transistor, connected in series between the substrate and the ground terminal, with the substrate side as an anode and the ground side as a cand. 42
A coupling capacitor 43 is inserted between the connection point A of the waveform shaping section 30 and the output section of the waveform shaping section 30.
Pumping operation is performed according to the output of 0, and the substrate potential V
It has the function of pulling down the sub.

以上のよろに構成された本実施例に係る基板電位設定回
路によれば、基板電位V m u bが所定のスレッシ
ールド電位V.。−thよりも増加したときには、発振
部20が短い周期で発振動作を行うので、基板電位発生
ポンプ回路部40は基板電位を急速に低下させ、基板電
位V subをV mum−。よりも低いレベルまで引
き下げる。
According to the substrate potential setting circuit according to the present embodiment configured as described above, the substrate potential V mu b is set to a predetermined threshold potential V. . -th, the oscillation unit 20 performs an oscillation operation in a short period, so the substrate potential generation pump circuit unit 40 rapidly lowers the substrate potential to reduce the substrate potential Vsub to Vmum-. lower to a lower level.

基板電位v.ubが所定のスレッシロルド電位?.ub
−■を下回ると、発振部20が長い周期で発振動作を行
なうので、基板電位発生ポンプ回路部40は、基板電位
V■ゎを現状電位に維持する。
Substrate potential v. Is ub a predetermined threshold potential? .. ub
When the voltage falls below -■, the oscillation section 20 performs an oscillation operation in a long period, so the substrate potential generation pump circuit section 40 maintains the substrate potential V■ at the current potential.

このように、本実施例の回路によれば、基板電位を常に
一定の電位に維持することができる。
In this way, according to the circuit of this embodiment, the substrate potential can always be maintained at a constant potential.

第3図は本発明の第2の実施例に係る基板電位設定回路
を示す図である。
FIG. 3 is a diagram showing a substrate potential setting circuit according to a second embodiment of the present invention.

この回路が第1図に示した回路と異なる点は、基板電位
検知部50の構成である。即ち、この実施例の基板電位
検知部50においては、出力段の増幅器13に代えて、
接続点Bを入力とするPチャネル型MOS}ランジスタ
51及びNチャネル型MOS}ランジスタ52からなる
CMOSインパータ回路と、その出力側に設けられたイ
ンパータ53と、このインパータ53の入力端子と接地
端子との間に介挿され、ゲートが上記インパータ53の
出力と接続されたNチャネル型MOS}ランジスタ64
とを設けている。
This circuit differs from the circuit shown in FIG. 1 in the configuration of the substrate potential detection section 50. That is, in the substrate potential detection section 50 of this embodiment, instead of the output stage amplifier 13,
A CMOS inverter circuit consisting of a P-channel MOS transistor 51 and an N-channel MOS transistor 52 with connection point B as an input, an inverter 53 provided on its output side, and an input terminal and a ground terminal of this inverter 53. an N-channel MOS} transistor 64 inserted between the
and.

この回路によれば、基板電位検知部50のDC伝達特性
が、第4図に示すように、基板電位?■ゎ−。を中心と
して±ΔVのヒステリシス特性を持つことになるので、
基板電位vllubが予め設定された電位V sub−
。を中心として微小変動を起こした場合でも、その出力
VO1が振動することがなく、基板電位設定回路全体の
動作を安定させることができる。
According to this circuit, the DC transfer characteristic of the substrate potential detection section 50 is as shown in FIG. ■ゎ-. It will have a hysteresis characteristic of ±ΔV around .
The substrate potential vllub is a preset potential Vsub-
. Even if a small fluctuation occurs around , the output VO1 will not oscillate, and the operation of the entire substrate potential setting circuit can be stabilized.

[発明の効果コ 以上述べたように、本発明によれば、半導体集積回路の
基板電位を基板電位検知部で検知して、その検出結果に
基づいてポンビング動作を制御するようにしたから、基
板電位を常に一定の電位に固定することができ、半導体
集積回路の動作の安定化を図ることができるという効果
を奏する。
[Effects of the Invention] As described above, according to the present invention, the substrate potential of the semiconductor integrated circuit is detected by the substrate potential detection section, and the pumping operation is controlled based on the detection result. This has the effect that the potential can always be fixed at a constant potential, and the operation of the semiconductor integrated circuit can be stabilized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例に係る基板電位設定回路
のブロック図、第2図は同基板電位設定回路における基
板電位検知部の直流伝達特性を示す特性図、第3図は本
発明の第2の実施例に係る基板電位設定回路のブロック
図、第4図は同基板電位設定回路における基板゛電位検
知部の直流伝達特性を示す特性図、第5図は従来の基板
電位設定回路のブロック図である。 10.50;基板電位検知部、11;抵抗、12.51
;Pチャネノレ型MOS}ランジスタ、13;増幅器、
20;発振部、21乃至23.31乃至34,53.8
1乃至63;インバータ、30;波形整形部、40;基
板電位発生ポンプ回路部、41.42;ダイオード、4
3;結合キャパシタ、60;基板電位設定制御部
FIG. 1 is a block diagram of a substrate potential setting circuit according to the first embodiment of the present invention, FIG. 2 is a characteristic diagram showing the DC transfer characteristics of the substrate potential detection section in the same substrate potential setting circuit, and FIG. 3 is a diagram of the present invention. A block diagram of a substrate potential setting circuit according to a second embodiment of the invention, FIG. 4 is a characteristic diagram showing the DC transfer characteristics of the substrate potential detection section in the same substrate potential setting circuit, and FIG. 5 is a diagram showing a conventional substrate potential setting circuit. It is a block diagram of a circuit. 10.50; Substrate potential detection unit, 11; Resistance, 12.51
; P-channel type MOS} transistor, 13; amplifier,
20; Oscillation section, 21 to 23.31 to 34, 53.8
1 to 63; Inverter, 30; Waveform shaping section, 40; Substrate potential generation pump circuit section, 41.42; Diode, 4
3; Coupling capacitor, 60; Substrate potential setting control section

Claims (1)

【特許請求の範囲】[Claims] (1)半導体集積回路装置の基板電位を検出し基板電位
に応じた信号を出力する基板電位検知部と、この基板電
位検知部から出力される上記基板電位に応じた信号によ
って発振周波数が制御される発振部と、この発振部から
の出力に応じて基板の電荷を引き抜く基板電位発生ポン
プ回路部とを具備してなることを特徴とする基板電位設
定回路。
(1) The oscillation frequency is controlled by a substrate potential detection section that detects the substrate potential of the semiconductor integrated circuit device and outputs a signal corresponding to the substrate potential, and a signal corresponding to the substrate potential output from this substrate potential detection section. 1. A substrate potential setting circuit comprising: an oscillating section; and a substrate potential generating pump circuit section that extracts charge from the substrate in accordance with an output from the oscillating section.
JP1158525A 1989-06-21 1989-06-21 Substrate potential setting circuit Expired - Fee Related JP2841480B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1158525A JP2841480B2 (en) 1989-06-21 1989-06-21 Substrate potential setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1158525A JP2841480B2 (en) 1989-06-21 1989-06-21 Substrate potential setting circuit

Publications (2)

Publication Number Publication Date
JPH0323659A true JPH0323659A (en) 1991-01-31
JP2841480B2 JP2841480B2 (en) 1998-12-24

Family

ID=15673642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1158525A Expired - Fee Related JP2841480B2 (en) 1989-06-21 1989-06-21 Substrate potential setting circuit

Country Status (1)

Country Link
JP (1) JP2841480B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04368691A (en) * 1991-06-17 1992-12-21 Samsung Electron Co Ltd Back bias level sensing circuit for semiconductor device
US6459327B1 (en) * 1991-12-09 2002-10-01 Oki Electric Industry Co., Ltd. Feedback controlled substrate bias generator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694654A (en) * 1979-12-27 1981-07-31 Toshiba Corp Generating circuit for substrate bias voltage
JPS62190746A (en) * 1986-02-17 1987-08-20 Sanyo Electric Co Ltd Substrate-bias generating circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694654A (en) * 1979-12-27 1981-07-31 Toshiba Corp Generating circuit for substrate bias voltage
JPS62190746A (en) * 1986-02-17 1987-08-20 Sanyo Electric Co Ltd Substrate-bias generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04368691A (en) * 1991-06-17 1992-12-21 Samsung Electron Co Ltd Back bias level sensing circuit for semiconductor device
US6459327B1 (en) * 1991-12-09 2002-10-01 Oki Electric Industry Co., Ltd. Feedback controlled substrate bias generator

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