JPS6346573B2 - - Google Patents
Info
- Publication number
- JPS6346573B2 JPS6346573B2 JP54007982A JP798279A JPS6346573B2 JP S6346573 B2 JPS6346573 B2 JP S6346573B2 JP 54007982 A JP54007982 A JP 54007982A JP 798279 A JP798279 A JP 798279A JP S6346573 B2 JPS6346573 B2 JP S6346573B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- insulating film
- metal
- film
- probe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000523 sample Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000576 coating method Methods 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 10
- 239000012212 insulator Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 241001422033 Thestylus Species 0.000 description 3
- 239000010407 anodic oxide Substances 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置にかかり、とくに半導体基
板上に製作されたTr又はICのボンデイングパツ
ドに金属性探針を接触させて特性検査を行う時該
ボンデイングパツド下の絶縁酸化膜に生じるクラ
ツクを防ぐ半導体基板を有する半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular, when a metal probe is brought into contact with a bonding pad of a transistor or IC manufactured on a semiconductor substrate to inspect its characteristics, the characteristics of the bonding pad under the bonding pad are inspected. The present invention relates to a semiconductor device having a semiconductor substrate that prevents cracks from occurring in an insulating oxide film.
半導体装置で金属配線の方法とその表面保護方
法には、第１図ａに示すように半導体基板４上の
絶縁酸化膜３の上に蒸着で形成した金属被膜２を
陽極酸化により配線部以外の金属領域と配線部の
金属被膜上面とを金属酸化膜１に変えるもの、あ
るいは第１図ｂに示すように金属被膜２を写真腐
食技術で配線後シリコン酸化膜やチツ化膜等の絶
縁物被膜５で覆う方法が一般的に普及している。
この様にして製作された金属配線の中で外部電極
との接続や特性検査用にボンデイングパツド（以
下BPと略記）２が設けられている。このBPには
第３図ａに示す平面形状が角型のものや第４図ａ
に示す丸型のものがあり、その一辺及び直径は数
十μｍから百数十μｍ程度に、又BP上の保護膜
１，５はBPの端から5μｍ以上で10μｍより小さ
い（d1）内側を除去するように従来は設計されて
いた。この様な設計のBPに自動プローバー等を
使用した金属性探針６を接触させて特性検査を行
う工程があるが、該自動プローバーの装置の設定
から通常、金属探針には圧力（以下針圧と略記）
が加わる。したがつてAlやAuで出来ているBPの
金属被膜２は突き抜かれてBP下の絶縁酸化膜３
（金属配線と半導体基板とを分離する為の酸化膜）
に達し、さらに金属性探針の弾力性から該絶縁酸
化膜より柔かい金属被膜の横方向へとすべつてし
まう。この様子を第１図Ｃの金属性探針６′→６
の動きで示す。金属性探針６がBPの中央付近に
位置合わせされている場合には数十μｍ程度の横
すべりがあつても特に影響はないが、金属性探針
がBPの端の方へ位置合わせになると針圧による
横すべりは前記絶縁被膜１，５の壁８でストツプ
する。そしてストツプすることにより、これまで
横方向と下方向へと二分されていた針圧は下方向
だけに集中し、BPの絶縁酸化膜には針圧に耐え
きれず、クラツク７が生じてしまう。クラツクの
生じたBPに電圧が印加されると、BPの金属はマ
イグレーションによりBP下の半導体基板に短絡
してしまい不良Tr、や不良ICを作ることになり、
歩留を著るしく低下させた。 As shown in FIG. 1A, a method for forming metal wiring in a semiconductor device and a method for protecting its surface include a metal coating 2 formed by vapor deposition on an insulating oxide film 3 on a semiconductor substrate 4, and then anodizing the metal coating 2 in areas other than the wiring areas. The metal area and the upper surface of the metal coating of the wiring part are changed to a metal oxide film 1, or as shown in FIG. The method of covering with 5 is generally popular.
A bonding pad (hereinafter abbreviated as BP) 2 is provided in the metal wiring fabricated in this manner for connection with external electrodes and for testing characteristics. Some of these BPs have a rectangular planar shape as shown in Figure 3a, and others have a square planar shape as shown in Figure 4a
There is a round type shown in the figure, and the side and diameter are from several tens of μm to about 100-odd μm, and the protective films 1 and 5 on the BP are 5 μm or more from the edge of the BP and smaller than 10 μm (d 1 ) inside. It was previously designed to eliminate the There is a process in which characteristics are inspected by bringing a metal probe 6 using an automatic prober or the like into contact with a BP designed like this. However, due to the settings of the automatic prober device, the metal probe is usually under pressure (hereinafter referred to as needle). (abbreviated as pressure)
is added. Therefore, the metal film 2 of the BP made of Al or Au is penetrated and the insulating oxide film 3 under the BP is formed.
(Oxide film to separate metal wiring and semiconductor substrate)
, and furthermore, due to the elasticity of the metal probe, it slides in the lateral direction of the metal coating, which is softer than the insulating oxide film. This situation can be seen from the metallic probe 6' to 6 in Figure 1C.
It is shown by the movement of If the metal probe 6 is aligned near the center of the BP, there will be no particular effect even if there is a side slip of several tens of μm, but if the metal probe 6 is aligned toward the edge of the BP, Lateral slippage due to needle pressure is stopped at the wall 8 of the insulating coatings 1 and 5. Then, by stopping, the stylus pressure, which was previously divided into lateral and downward directions, is concentrated only in the downward direction, and the insulating oxide film of the BP cannot withstand the stylus pressure, resulting in crack 7. When a voltage is applied to a BP with a crack, the metal of the BP migrates and short-circuits to the semiconductor substrate under the BP, creating a defective transistor or IC.
Yield was significantly reduced.
本発明の目的は上記欠点を除去した有効な半導
体装置を提供することである。 An object of the present invention is to provide an effective semiconductor device that eliminates the above-mentioned drawbacks.
本発明はボンデイングパツド上に形成された絶
縁物被膜の除去ラインから該ボンデイングパツド
の一部又は全域を10μｍ以上広く形成することを
特徴とする半導体装置である。 The present invention is a semiconductor device characterized in that a part or the entire area of the bonding pad is formed wider by 10 μm or more from the removal line of the insulating film formed on the bonding pad.
すなわち本発明の特徴は、半導体基板の主面に
設けられた第１の絶縁膜と、前記第１の絶縁膜上
に被着して設けられた金属被膜からなりかつ、そ
の全領域の上表面が平坦なボンデイングパツド
と、前記第１の絶縁膜に被着しかつ前記ボンデイ
ングパツドの端部より該ボンデイングパツドの上
表面の上を該上表面に被着して延在する第２の絶
縁膜と、前記第２の絶縁膜に設けられ、前記ボン
デイングパツドの上表面の中央部を露出する開口
とを有する半導体装置において、前記ボンデイン
グパツドの端部とそれに対向する前記開口の端部
との距離は、該ボンデイングパツドの全域におい
て10μｍ以上広くなつており、このように10μｍ
以上広く上表面に前記第２の絶縁膜を被着するこ
とにより、特性検査用の探針が前記ボンデイング
パツドの上表面に圧接し全領域が平坦な該上表面
を横すべりをした際に、探針が前記第２の絶縁膜
の開口の端部に達した後も前記第２の絶縁膜下の
前記金属被膜のボンデイングパツド上を横すべり
し、かつ、該探針が該ボンデイングパツドの端部
まで達しないようにした半導体装置にある。 That is, the present invention is characterized by comprising a first insulating film provided on the main surface of a semiconductor substrate, and a metal coating provided on the first insulating film, and covering the entire upper surface of the first insulating film. a flat bonding pad, and a second insulating film attached to the first insulating film and extending from an end of the bonding pad over the upper surface of the bonding pad. an insulating film, and an opening provided in the second insulating film to expose a central portion of the upper surface of the bonding pad, the edge of the bonding pad and the opening opposite thereto; The distance from the end portion is wider than 10 μm over the entire area of the bonding pad, and as shown,
By depositing the second insulating film over a wide area of the upper surface, when the probe for characteristic testing comes into pressure contact with the upper surface of the bonding pad and slides across the entire flat upper surface, Even after the probe reaches the end of the opening in the second insulating film, the probe continues to slide sideways on the bonding pad of the metal film under the second insulating film, and the probe remains on the bonding pad of the metal coating under the second insulating film. This is in a semiconductor device that does not reach the edge.
次に本発明の実施例を説明する。 Next, embodiments of the present invention will be described.
第２図ａ，ｂのようにBP上の絶縁物被膜１，
５の除去面積は従来のままにしBPの面積を広げ
ると（d1からd2へ）、BP上絶縁物被膜の除去ライ
ン付近に金属性探針の位置がきても、BPと絶縁
物被膜との境界の壁８は遠く離れているのでBP
下の絶縁酸化膜３へ針圧は弱く、横すべりだけで
クラツクには至らないで済む。又、BP上の絶縁
物被膜のd2の部分は、柔かい金属被膜の上にある
ので金属性探針の横すべりを停められることはな
い。このBPを広げる大きさはBP上絶縁物被膜除
去ラインからの距離d2を10μｍ以上で内部配線に
影響のないところまでとすればよい。この設計は
BPが角型の場合は本発明では第３図ｂのように
四辺の全方向において、10μｍ以上のd2とする。
その形状はBP上絶縁物被膜除去ラインと平行で
なくとも任意の形状でよい。又、丸型の場合も第
４図ｂ，ｃの様に同心円上に広げたものや、偏心
させて広げたもの等任意の形状でよいが、いずれ
の場合も全周にわたり10μｍ以上である必要があ
る。 As shown in Figure 2 a and b, the insulating film 1 on the BP,
If the removal area in step 5 remains the same as before and the area of BP is increased (from d 1 to d 2 ), even if the metal probe is positioned near the removal line of the insulator film on the BP, the BP and the insulator film will be separated. Since the boundary wall 8 is far away, BP
The stylus pressure on the underlying insulating oxide film 3 is weak, and only sideways slipping does not result in a crack. Furthermore, since the d2 portion of the insulating film on the BP is on a soft metal film, the sideways sliding of the metal probe cannot be stopped. The extent to which this BP is widened is such that the distance d 2 from the insulating film removal line on the BP is 10 μm or more and does not affect internal wiring. This design
In the case where the BP is square, in the present invention, d2 is set to be 10 μm or more in all directions of the four sides as shown in FIG. 3b.
The shape may be any shape, even if it is not parallel to the insulator film removal line on the BP. Also, in the case of a round shape, it may be of any shape, such as one spread out concentrically as shown in Figure 4 b and c, or spread out eccentrically, but in either case, it must be 10 μm or more over the entire circumference. There is.
以上の様な設計変更により、歩留は向上し、品
質面に関しても非常に改善され、工業上大きな利
益がある。 The above-mentioned design changes improve the yield and greatly improve the quality, resulting in great industrial benefits.
第１図ａおよび第１図ｂはそれぞれ従来技術に
よる半導体装置を示す断面図であり、第１図ｃは
これら半導体装置の欠点を説明する断面図であ
る。第２図ａおよび第２図ｂはそれぞれ本発明の
実施例を示す断面図である。第３図ａおよび第４
図ａはそれぞれ従来技術のボンデイングパツド部
を示す平面図であり、第３図ｂ、第４図ｂおよび
第４図ｃはそれぞれ本発明のボンデイングパツド
部を示す平面図である。
尚、図において、１は陽極酸化膜、２は金属被
膜、３は絶縁酸化膜、４は半導体基板、５は絶縁
物被膜、６は金属性探針、７はクラツク、８は金
属被膜と接する絶縁物被膜の横方向の壁である。
FIGS. 1a and 1b are sectional views showing semiconductor devices according to the prior art, and FIG. 1c is a sectional view illustrating the drawbacks of these semiconductor devices. FIGS. 2a and 2b are cross-sectional views showing embodiments of the present invention, respectively. Figures 3a and 4
Figure a is a plan view of a prior art bonding pad, and Figures 3b, 4b and 4c are plan views of a bonding pad of the present invention. In the figure, 1 is an anodic oxide film, 2 is a metal coating, 3 is an insulating oxide film, 4 is a semiconductor substrate, 5 is an insulator coating, 6 is a metal probe, 7 is a crack, and 8 is in contact with a metal coating. This is the lateral wall of the insulation coating.
Claims (1)
と、前記第１の絶縁膜上に被着して設けられた金
属被膜からなりかつ、その全領域の上表面が平坦
なボンデイングパツドと、前記第１の絶縁膜に被
着しかつ前記ボンデイングパツドの端部より該ボ
ンデイングパツドの上表面の上を該上表面に被着
して延在する第２の絶縁膜と、前記第２の絶縁膜
に設けられ、前記ボンデイングパツドの上表面の
中央部を露出する開口とを有する半導体装置にお
いて、前記ボンデイングパツドの端部とそれに対
向する前記開口の端部との距離は、該ボンデイン
グパツドの全域において10μｍ以上広くなつてお
り、このように10μｍ以上広く上表面に前記第２
の絶縁膜を被着することにより、特性検査用の探
針が前記ボンデイングパツドの上表面に圧接し全
領域が平坦な該上表面を横すべりをした際に、探
針が前記第２の絶縁膜の開口の端部に達した後も
前記第２の絶縁膜下の前記金属被膜のボンデイン
グパツド上を横すべりし、かつ、該探針が該ボン
デイングパツドの端部まで達しないようにしたこ
とを特徴とする半導体装置。1. A bonding pad consisting of a first insulating film provided on the main surface of a semiconductor substrate and a metal film deposited on the first insulating film, and having a flat upper surface over the entire area thereof. a second insulating film deposited on the first insulating film and extending from an end of the bonding pad over the upper surface of the bonding pad; In a semiconductor device having an opening provided in a second insulating film and exposing a central portion of the upper surface of the bonding pad, the distance between an end of the bonding pad and an end of the opening opposite thereto is , the bonding pad has a width of 10 μm or more over the entire area, and the second pad has a width of 10 μm or more on the upper surface.
By depositing an insulating film of Even after reaching the end of the opening in the film, the probe continued to slide sideways on the bonding pad of the metal film under the second insulating film, and the probe was prevented from reaching the end of the bonding pad. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP798279A JPS5599769A (en) | 1979-01-25 | 1979-01-25 | Semicondcutor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP798279A JPS5599769A (en) | 1979-01-25 | 1979-01-25 | Semicondcutor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5599769A JPS5599769A (en) | 1980-07-30 |
| JPS6346573B2 true JPS6346573B2 (en) | 1988-09-16 |
Family
ID=11680637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP798279A Granted JPS5599769A (en) | 1979-01-25 | 1979-01-25 | Semicondcutor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5599769A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4870475A (en) * | 1971-12-23 | 1973-09-25 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5353969U (en) * | 1976-10-08 | 1978-05-09 |
-
1979
- 1979-01-25 JP JP798279A patent/JPS5599769A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4870475A (en) * | 1971-12-23 | 1973-09-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5599769A (en) | 1980-07-30 |
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