JPH02156640A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02156640A JPH02156640A JP63311204A JP31120488A JPH02156640A JP H02156640 A JPH02156640 A JP H02156640A JP 63311204 A JP63311204 A JP 63311204A JP 31120488 A JP31120488 A JP 31120488A JP H02156640 A JPH02156640 A JP H02156640A
- Authority
- JP
- Japan
- Prior art keywords
- film
- nitride film
- plasma nitride
- bonding pad
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000002161 passivation Methods 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000001947 vapour-phase growth Methods 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 abstract description 32
- 238000000034 method Methods 0.000 abstract description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 3
- 230000008569 process Effects 0.000 abstract description 3
- 230000009545 invasion Effects 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000007743 anodising Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000000088 plastic resin Substances 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にパッシベーション膜の
構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a passivation film.
従来、半導体装置の最外殻部分には、外部環境から半導
体装置を保護する目的で、パッシベーション膜が形成さ
れている。通常、このパッシベーション膜には低温成長
が可能な気相成長法を用いてシリコン窒化膜あるいはシ
リコン酸化膜などが使われている。Conventionally, a passivation film is formed on the outermost shell of a semiconductor device for the purpose of protecting the semiconductor device from the external environment. Typically, this passivation film is made of a silicon nitride film, a silicon oxide film, or the like using a vapor phase growth method that allows low-temperature growth.
第３図は従来技術によるアルミ配線とパッシベーション
膜の構造を示した断面図である。すなわち、シリコン基
板１１上に酸化シリコン膜１２を形成したのち、アルミ
配線２３を形成したのち、全面にプラズマＣＶＤ法によ
る窒化膜（以下プラズマ窒化膜という）１４を形成する
。このように形成されたプラズマ窒化膜１４のアルミ配
線２３の側壁部でのカバレッジは悪く、側壁最薄部のカ
バレッジは、平坦部の膜厚より薄い。素子が微細化され
、アルミ配線２３の間隔が狭くなるはど、アルミ配線２
３の側壁でのプラズマ窒化膜１４の膜厚は薄くなり、パ
ッシベーション性は悪化する。FIG. 3 is a cross-sectional view showing the structure of aluminum wiring and a passivation film according to the prior art. That is, after a silicon oxide film 12 is formed on a silicon substrate 11, an aluminum wiring 23 is formed, and a nitride film (hereinafter referred to as a plasma nitride film) 14 is formed on the entire surface by plasma CVD. The coverage of the plasma nitride film 14 formed in this manner on the side wall portion of the aluminum wiring 23 is poor, and the coverage at the thinnest portion of the side wall is thinner than the film thickness at the flat portion. As elements become finer and the intervals between the aluminum wiring lines 23 become narrower, the aluminum wiring lines 2
The thickness of the plasma nitride film 14 on the sidewalls 3 becomes thinner, and the passivation properties deteriorate.
このようなパッシベーション性の悪化を防ぐ手段として
、従来シリコンを主成分とする液を塗布・焼成して素子
表面を平坦化する方法が試みられて来た。第４図は塗布
・焼成膜をパッシベーション膜に用いた半導体装置の断
面図であり、１１は半導体基板、１２は酸化シリコン膜
、１３はアルミ配線、１４Ａ、１４Ｂはプラズマ窒化膜
、１５は塗布・焼成膜である。かかる構造を用いると、
通常の配線領域は素子表面が平滑化され、パッシベーシ
ョン膜のぜい弱部分がなくなり、素子の信頼性は著しく
向上する。As a means to prevent such deterioration of passivation properties, attempts have been made to planarize the element surface by coating and baking a liquid containing silicon as a main component. FIG. 4 is a cross-sectional view of a semiconductor device using a coated and fired film as a passivation film, in which 11 is a semiconductor substrate, 12 is a silicon oxide film, 13 is an aluminum wiring, 14A and 14B are plasma nitride films, and 15 is a coated and fired film. It is a fired film. With such a structure,
In the normal wiring region, the element surface is smoothed, the weak parts of the passivation film are eliminated, and the reliability of the element is significantly improved.
この構造のボンディングパッド部分の断面図を第５図に
示す。ボンディングパッド１３上は、外部回路と接続す
るためパッシベーション膜に開孔が設けられているが、
その開孔側壁部に塗布・焼成膜１５が露出する構造とな
っている。A cross-sectional view of the bonding pad portion of this structure is shown in FIG. On the bonding pad 13, an opening is provided in the passivation film for connection to an external circuit.
The structure is such that the coated and fired film 15 is exposed on the side wall of the opening.
塗布・焼成膜１５は、アルミニウムからなるボンディン
グパッド１３が許容し得る最高温度で焼成されるが、そ
の温度は高々５００℃以下である。この程度の温度では
、塗布・焼成膜１５は十分に安定な膜にはなっていない
。すなわち、通常多孔質な膜であり、湿気を吸収し水分
を素子内部へ速やかに運搬する導水路の役割をはたす。The coated and fired film 15 is fired at the highest temperature that the bonding pad 13 made of aluminum can tolerate, and the temperature is at most 500°C or less. At this temperature, the coated and fired film 15 is not sufficiently stable. That is, it is usually a porous membrane, and serves as a water conduit that absorbs moisture and quickly transports the moisture into the inside of the element.
このため、第４図に示した構造では、半導体装置上面か
らの水分浸入に対しては十分に強いパッシベーション性
を発揮するが、第５図に示した構造ではボンディングパ
ッド部からの水分の浸入に対しては極めて弱い。Therefore, the structure shown in FIG. 4 exhibits a sufficiently strong passivation property against moisture intrusion from the top surface of the semiconductor device, but the structure shown in FIG. It is extremely weak against
第５図に示した半導体装置の構造を改善したものが第６
図に示す構造のものであり、ボンディングパッド１３上
におけるパッシベーション膜の側面にプラズマ窒化膜１
７を設けたものである。その製造方法としては、第５図
に示した構造を得た後に、更にプラズマ窒化膜１７を成
長させ、このプラズマ窒化膜１７を平行平板型ドライエ
ツチング法でエツチング除去することにより開孔側壁に
のみプラズマ窒化膜１７を残すことができる。The sixth device is an improved structure of the semiconductor device shown in FIG.
The structure shown in the figure has a plasma nitride film 1 on the side surface of the passivation film on the bonding pad 13.
7. The manufacturing method is to further grow a plasma nitride film 17 after obtaining the structure shown in FIG. The plasma nitride film 17 can remain.
一ヒ述した従来の半導体装置におけるパッシベーション
膜では、第６図に示したように、ボンディングパッド１
３上のパッシベーション膜の側面にプラズマ窒化膜１７
が存在するため、半導体装置の信頼性は多少向上してい
る。しかし、プラズマ窒化膜１７の形成は制御が難しい
。特に、側面に残すプラズマ窒化膜１７の膜厚を精度よ
く再現させるのは、大きな困難を伴う。側面のプラズマ
窒化膜１７の膜厚が薄くなると、水分は容易に塗布・焼
成ｖ１５側へ浸入し、ひいては容易に半導体内部にまで
水分が浸入し、半導体装置の劣化を防ぐことが極めて困
難になるという欠点がある。In the passivation film in the conventional semiconductor device described above, as shown in FIG.
A plasma nitride film 17 is formed on the side surface of the passivation film on 3.
Due to the existence of the above, the reliability of the semiconductor device is improved to some extent. However, the formation of the plasma nitride film 17 is difficult to control. In particular, it is very difficult to accurately reproduce the thickness of the plasma nitride film 17 left on the side surfaces. When the thickness of the plasma nitride film 17 on the side surface becomes thinner, moisture easily infiltrates into the coating/baking v15 side and, in turn, easily infiltrates into the inside of the semiconductor, making it extremely difficult to prevent deterioration of the semiconductor device. There is a drawback.
本発明の半導体装置は、半導体基板上に絶縁膜を介して
形成されたボンディングパッドと、前記ボンディングパ
ッド上の周辺部に形成されたシリコンを主成分とする溶
液を塗布・焼成した第１の絶縁膜と気相成長法により形
成した第２の絶縁膜からなるパッシベーション膜と、前
記ボンディングパッド上の前記パッシベーション膜の側
面に形成された気相成長法による第３の絶縁膜とを有す
る半導体装置において、前記パッシベーション膜の側面
における前記第１の絶縁膜は前記第２の絶縁膜に対して
アンダーカット部を有するものである。The semiconductor device of the present invention includes a bonding pad formed on a semiconductor substrate via an insulating film, and a first insulating layer formed around the bonding pad by applying and baking a solution containing silicon as a main component. A semiconductor device having a passivation film made of a film and a second insulating film formed by a vapor phase growth method, and a third insulating film formed by a vapor growth method on a side surface of the passivation film on the bonding pad. The first insulating film on the side surface of the passivation film has an undercut portion with respect to the second insulating film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の製造方法を説明するた
めの半導体チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip for explaining the manufacturing method of the first embodiment of the present invention.
まず、第１図（ａ＞に示す如く、シリコン基板ｌｌ上に
酸化シリコン膜１２を形成し、膜厚１μｍのアルミ配線
に接続するボンディングパッド１３を形成する。次に、
パッシベーション膜として、厚さ５０００人のプラズマ
窒化膜１４Ａと厚さ２０００人のシリコンを主成分とす
る塗布・焼成膜１５と、厚さ５０００のプラズマ窒化ｐ
ｌＡ１４Ｂとを形成する。次に、ボンディングパッド１
３の部分を平行平板型ドライエツチング法を用いて開孔
する。First, as shown in FIG. 1(a), a silicon oxide film 12 is formed on a silicon substrate 11, and a bonding pad 13 connected to an aluminum wiring with a film thickness of 1 μm is formed.Next,
As passivation films, a plasma nitride film 14A with a thickness of 5,000 μm, a coated and fired film 15 mainly composed of silicon with a thickness of 2,000 μm, and a plasma nitride film 14A with a thickness of 5,000 μm are used.
form lA14B. Next, bonding pad 1
A hole is formed in the portion No. 3 using a parallel plate dry etching method.
次に、希釈フッ化水素酸で塗布・焼成膜１５を１μｍエ
ツチングする。このとき、プラズマ窒化膜１４Ａ、１４
Ｂは殆んどエツチングされないのて、開孔部側面形状は
塗布・焼成膜１５の部分だけが１μｍ後退しアンダーカ
ット部１６が形成される。この状態で全面に再度プラズ
マ窒化Ｍ１７を６０００人の厚さに形成する。プラズマ
窒化膜はカバレッジが良いので、アンダーカット部１６
にも十分な膜厚のプラズマ窒化膜が形成される。Next, the coated and fired film 15 is etched by 1 μm using diluted hydrofluoric acid. At this time, plasma nitride films 14A, 14
Since B is hardly etched, only the coated and fired film 15 is recessed by 1 μm in the side shape of the opening, and an undercut portion 16 is formed. In this state, plasma nitride M17 is again formed on the entire surface to a thickness of 6000 mm. Since the plasma nitride film has good coverage, the undercut portion 16
A plasma nitride film with a sufficient thickness is formed.
この状態で平行平板型ドライエツチング法でプラズマ窒
化膜１７を異方性エツチングすると、第１図（ｂ）に示
す如く、プラズマ窒化膜１７がパッシベーション膜の側
面に残る。In this state, when the plasma nitride film 17 is anisotropically etched using a parallel plate dry etching method, the plasma nitride film 17 remains on the side surfaces of the passivation film, as shown in FIG. 1(b).
このように構成された第１の実施例によれば、塗布・焼
成膜１５は十分に厚いプラズマ窒化膜１７で側面部を保
護されているので、水分の浸入に対して極めて強い構造
の半導体装置が得られ信頼性は向上する。According to the first embodiment configured in this manner, the side surfaces of the coated and fired film 15 are protected by the sufficiently thick plasma nitride film 17, so that the semiconductor device has a structure that is extremely resistant to moisture intrusion. is obtained and reliability is improved.
更に本第１の実施例によれば、第１の実施例と同等の信
頼性を得るための、例えば金属配線形成の如き高価なプ
ロセスを用いる必要がないので、コストが安く、製造の
納期短縮化、プロセスの容易さ故の製造良品率の向上な
どを図ることができる。Furthermore, according to the first embodiment, there is no need to use expensive processes such as metal wiring formation in order to obtain the same reliability as in the first embodiment, so the cost is low and the manufacturing delivery time is shortened. It is possible to improve the production rate of non-defective products due to the ease of the process.
第７図は、従来構造の半導体装置と、本発明の実施例の
信頼性試験をシリコンウェーハ状態で行った結果を示す
図である。試験環境は、１２５℃、湿度１００％、２．
２気圧の条件で行った。不良率の判定は、ボンディング
パッドから１０１００ｔｔれた場所でのアルミ配線の腐
蝕の有無で行った。FIG. 7 is a diagram showing the results of a reliability test conducted on a semiconductor device having a conventional structure and an embodiment of the present invention in a silicon wafer state. The test environment was 125°C, 100% humidity, 2.
The test was carried out under the condition of 2 atmospheres. The defective rate was determined based on the presence or absence of corrosion of the aluminum wiring at a location 10,100 tt away from the bonding pad.
第５図に示した従来例では、１２時間以内に不良が発生
し、２４時間後にはほぼ全数不良となった。改善された
従来技術である第６図に示した従来例では、はぼ１００
％不良になるまでに約６０時間を要している。しかし、
ここで特徴的なことは、試験の初期段階で約１０％の不
良が既に発生していることである。これは、第６図に示
したプラズマ窒化膜１７の制御が困難であり、部分的に
薄いところが出来、そこから水分が浸入したためと考え
られる。In the conventional example shown in FIG. 5, defects occurred within 12 hours, and almost all the products were defective after 24 hours. In the conventional example shown in FIG. 6, which is an improved conventional technique,
It takes about 60 hours to reach % failure. but,
What is characteristic here is that approximately 10% of defects have already occurred at the initial stage of the test. This is thought to be because it is difficult to control the plasma nitride film 17 shown in FIG. 6, and there are thin areas in some areas, through which moisture infiltrates.
それに反し、第１の実施例では４８時間まで不良がまっ
たくなく、顕著な改善が示されている。In contrast, the first example had no defects for up to 48 hours, indicating a significant improvement.
プラスチツブ樹脂等で保護されると、耐湿性は格段に向
上するので、第１図の構造であれば十分な耐湿性を有す
ると言える。When protected with plastic resin or the like, moisture resistance is greatly improved, so it can be said that the structure shown in FIG. 1 has sufficient moisture resistance.
第２図は本発明の第２の実施例の断面図である。シリコ
ン基板１１上には酸化シリコン膜１２を介してアルミ配
線に接続するボンディングパッド１３が形成されている
。そして、このボンディングパッド１３の周辺部には、
ボンディングパッド１３を陽極化成して形成されたアル
ミナ膜２４が形成されており、更にパッシベーション膜
としてアンダーカット部１６を有する塗布・焼成膜１５
の第１の絶縁膜とプラズマ窒化膜１４の第２の絶縁膜と
が形成されている。更にボンディングパッド１３上のパ
ッシベーション膜の側面には第３の絶縁膜としてプラズ
マ窒化膜１７が形成されている。FIG. 2 is a sectional view of a second embodiment of the invention. A bonding pad 13 is formed on the silicon substrate 11 to be connected to the aluminum wiring via a silicon oxide film 12. Then, around this bonding pad 13,
An alumina film 24 formed by anodizing the bonding pad 13 is formed, and a coated/fired film 15 having an undercut portion 16 as a passivation film is formed.
A first insulating film and a second insulating film of plasma nitride film 14 are formed. Furthermore, a plasma nitride film 17 is formed as a third insulating film on the side surface of the passivation film on the bonding pad 13.
このように構成された第２の実施例によれば、ボンディ
ングパッド１３を構成するへｌ膜がアルミナ膜２４によ
り覆われているなめ、窒化シリコン膜で直接覆われる場
合に比べ、耐湿性が向トすると共に、ストレスマイグレ
ーションによるへ！消−失の発生が極めて少くなるとい
う利点がある。According to the second embodiment configured as described above, since the aluminum film constituting the bonding pad 13 is covered with the alumina film 24, the moisture resistance is improved compared to the case where it is directly covered with the silicon nitride film. At the same time as stress migration! This has the advantage that the occurrence of loss is extremely reduced.
なお、塗布・焼成膜の性質にもよるが、アルミナＪＩ！
２４を無くし、塗布・焼成膜１５を直接ボンディング
パッド］３に接触させることも可能である。Although it depends on the properties of the coated and fired film, alumina JI!
It is also possible to omit 24 and bring the coated and fired film 15 into direct contact with the bonding pad]3.
更に、上記実施例においてはパッシベーション膜として
プラズマ窒化膜を用いた場合について説明したが、酸化
膜、オキシナイトライド膜、リンケイ酸カラス膜など目
的に応じた組合わせを用いることができる。Furthermore, in the above embodiments, the case where a plasma nitride film is used as the passivation film has been described, but a combination of an oxide film, an oxynitride film, a phosphosilicate glass film, etc. can be used depending on the purpose.
以上説明したように本発明は、ポンデイ〉′グパッド上
の周辺部に形成する塗布・焼成膜がらなる第１の絶縁膜
と気相成長法による第２の絶縁膜からなるパッシベーシ
ョン膜のうち、第１の絶縁膜にアンダーカット部を設け
ることにより、パッシベーション膜の側面に形成される
気相成長による第３の絶縁膜がこのアンダーカット部に
も形成されるため、半導体装置の耐水性が向上するとい
う効果がある。従って、信頼性の高い半導体装置を得る
ことができる。As explained above, the present invention provides a passivation film consisting of a first insulating film made of a coated and fired film formed on the periphery of a pump pad and a second insulating film formed by a vapor phase growth method. By providing an undercut part in the first insulating film, the third insulating film formed on the side surface of the passivation film by vapor phase growth is also formed in this undercut part, improving the water resistance of the semiconductor device. There is an effect. Therefore, a highly reliable semiconductor device can be obtained.
第１図及び第２図は本発明の第１及び第２の実施例の断
面図、第３図〜第６図は従来例を説明するための半導体
チップの断面図、第７図は耐湿性試験結果を示す図であ
る。
１１・・・シリコン基板、１２・・・酸化シリコン膜、
１３・・・ボンディングパッド、１４．１４Ａ、１４Ｂ
・・・プラズマ窒化膜、１５・・・塗布・焼成膜、１６
・・アンダーカット部、１７・・・プラズマ窒化膜、２
３・・・アルミ配線、２４・・・アルミナ膜。
Ｉ４：９北シリコン膜
Ｉ４： アルミカ腺
第２図
Ｉ４ニゲ２ズマ窒化膜
拓３０
＄４
第５図1 and 2 are cross-sectional views of the first and second embodiments of the present invention, FIGS. 3 to 6 are cross-sectional views of semiconductor chips for explaining conventional examples, and FIG. It is a figure showing a test result. 11... Silicon substrate, 12... Silicon oxide film,
13... Bonding pad, 14.14A, 14B
...Plasma nitride film, 15...Coating/baking film, 16
... Undercut portion, 17... Plasma nitride film, 2
3...Aluminum wiring, 24...Alumina film. I4:9 North silicon film I4: Aluminum gland Figure 2 I4 Nige 2 Zuma Nitride film 30 $4 Figure 5
Claims (1)
パッドと、前記ボンディングパッド上の周辺部に形成さ
れたシリコンを主成分とする溶液を塗布・焼成した第１
の絶縁膜と気相成長法により形成した第２の絶縁膜から
なるパッシベーション膜と、前記ボンディングパッド上
の前記パッシベーション膜の側面に形成された気相成長
法による第３の絶縁膜とを有する半導体装置において、
前記パッシベーション膜の側面における前記第１の絶縁
膜は前記第２の絶縁膜に対してアンダーカット部を有す
ることを特徴とする半導体装置。A bonding pad formed on a semiconductor substrate via an insulating film, and a first silicon-based solution formed on the periphery of the bonding pad coated and fired.
a passivation film consisting of an insulating film and a second insulating film formed by vapor phase growth; and a third insulating film formed by vapor growth on the side surface of the passivation film on the bonding pad. In the device,
A semiconductor device, wherein the first insulating film on a side surface of the passivation film has an undercut portion with respect to the second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63311204A JP2751274B2 (en) | 1988-12-09 | 1988-12-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63311204A JP2751274B2 (en) | 1988-12-09 | 1988-12-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02156640A true JPH02156640A (en) | 1990-06-15 |
| JP2751274B2 JP2751274B2 (en) | 1998-05-18 |
Family
ID=18014356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63311204A Expired - Lifetime JP2751274B2 (en) | 1988-12-09 | 1988-12-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2751274B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100702120B1 (en) * | 2001-06-30 | 2007-03-30 | 주식회사 하이닉스반도체 | Bonding PAD of semiconductor device and method for forming the same |
| KR100869112B1 (en) * | 2002-01-14 | 2008-11-17 | 삼성전자주식회사 | Reflective type liquid crystal display device and method of manufacturing the same |
-
1988
- 1988-12-09 JP JP63311204A patent/JP2751274B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100702120B1 (en) * | 2001-06-30 | 2007-03-30 | 주식회사 하이닉스반도체 | Bonding PAD of semiconductor device and method for forming the same |
| KR100869112B1 (en) * | 2002-01-14 | 2008-11-17 | 삼성전자주식회사 | Reflective type liquid crystal display device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2751274B2 (en) | 1998-05-18 |
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