JP2751274B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2751274B2 JP2751274B2 JP63311204A JP31120488A JP2751274B2 JP 2751274 B2 JP2751274 B2 JP 2751274B2 JP 63311204 A JP63311204 A JP 63311204A JP 31120488 A JP31120488 A JP 31120488A JP 2751274 B2 JP2751274 B2 JP 2751274B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- bonding pad
- semiconductor device
- plasma nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にパッシベーション膜
の構造に関する。The present invention relates to a semiconductor device, and more particularly, to a structure of a passivation film.
従来、半導体装置の最外穀部分には、外部環境から半
導体装置を保護する目的で、パッシベーション膜が形成
されている。通常、このパッシベーション膜には低温成
長が可能な気相成長法を用いてシリコン窒化膜あるいは
シリコン酸化膜などが使われている。Conventionally, a passivation film has been formed on the outermost grain portion of a semiconductor device for the purpose of protecting the semiconductor device from the external environment. Usually, a silicon nitride film or a silicon oxide film is used for the passivation film by using a vapor phase growth method capable of growing at a low temperature.
第３図は従来技術によるアルミ配線とパッシベーショ
ン膜の構造を示した断面図である。すなわち、シリコン
基板11上に酸化シリコン膜12を形成したのち、アルミ配
線23を形成したのち、全面にプラズマCVD法による窒化
膜（以下プラズマ窒化膜という）14を形成する。このよ
うに形成されたプラズマ窒化膜14のアルミ配線23の側壁
部でのカバレッジは悪く、側壁最薄部のカバレッジは、
平坦部の膜厚より薄い。素子が微細化され、アルミ配線
23の間隔が狭くなるほど、アルミ配線23の側壁でのプラ
ズマ窒化膜14の膜厚は薄くなり、パッシベーション性は
悪化する。FIG. 3 is a sectional view showing the structure of an aluminum wiring and a passivation film according to the prior art. That is, after a silicon oxide film 12 is formed on a silicon substrate 11, an aluminum wiring 23 is formed, and then a nitride film (hereinafter referred to as a plasma nitride film) 14 is formed on the entire surface by a plasma CVD method. The coverage of the plasma nitride film 14 thus formed on the side wall of the aluminum wiring 23 is poor, and the coverage of the thinnest side wall is:
Thinner than the thickness of the flat part. Elements are miniaturized, aluminum wiring
As the distance between the 23 becomes narrower, the film thickness of the plasma nitride film 14 on the side wall of the aluminum wiring 23 becomes thinner, and the passivation property deteriorates.
このようなパッシベーション性の悪化を防ぐ手段とし
て、従来シリコンを主成分とする液を塗布・焼成して素
子表面を平坦化する方法が試みられて来た。第４図は塗
布・焼成膜をパッシベーション膜に用いた半導体装置の
断面図であり、11は半導体基板、12は酸化シリコン膜、
13はアルミ配線、14A,14Bはプラズマ窒化膜、15は塗布
・焼成膜である。かかる構造を用いると、通常の配線領
域は素子表面が平滑化され、パッシベーション膜のぜい
弱部分がなくなり、素子の信頼性は著しく向上する。As a means for preventing such deterioration of the passivation property, a method of applying and baking a liquid containing silicon as a main component to flatten the element surface has been attempted. FIG. 4 is a cross-sectional view of a semiconductor device using a coating / baking film as a passivation film, where 11 is a semiconductor substrate, 12 is a silicon oxide film,
13 is an aluminum wiring, 14A and 14B are plasma nitride films, and 15 is a coating / firing film. When such a structure is used, the surface of the element is smoothed in a normal wiring region, the weak portion of the passivation film is eliminated, and the reliability of the element is remarkably improved.
この構造のボンディングパッド部分の断面図を第５図
に示す。ボンディングパッド13上は、外部回路と接続す
るためパッシベーション膜に開孔が設けられているが、
その開孔側壁部に塗布・焼成膜15が露出する構造となっ
ている。FIG. 5 is a sectional view of a bonding pad portion having this structure. On the bonding pad 13, an opening is provided in the passivation film to connect to an external circuit,
The structure is such that the coating / firing film 15 is exposed on the side wall of the opening.
塗布・焼成層15は、アルミニウムからなるボンディン
グパッド13が許容し得る最高温度で焼成されるが、その
温度は高々500℃以下である。この程度の温度では、塗
布・焼成膜15は十分に安定な膜にはなっていない。すな
わち、通常多孔質な膜であり、湿気を吸収し水分を素子
内部へ速やかに運搬する導水路の役割をはたす。このた
め、第４図に示した構造では、半導体装置上面からの水
分浸入に対しては十分に強いパッシベーション性を発揮
するが、第５図に示した構造ではボンディングパッド部
からの水分の浸入に対しては極めて弱い。The coating / firing layer 15 is fired at the maximum temperature allowable for the bonding pad 13 made of aluminum, and the temperature is at most 500 ° C. or less. At such a temperature, the applied / fired film 15 is not a sufficiently stable film. That is, the membrane is usually a porous membrane, and serves as a water conduit for absorbing moisture and quickly transporting moisture to the inside of the element. For this reason, the structure shown in FIG. 4 exhibits a sufficiently strong passivation property against moisture intrusion from the upper surface of the semiconductor device, but the structure shown in FIG. It is extremely weak.
第５図に示した半導体装置の構造を改善したものが第
６図に示す構造のものであり、ボンディングパッド13上
におけるパッシベーション膜の側面にプラズマ窒化膜17
を設けたものである。その製造方法としては、第５図に
示した構造を得た後に、更にプラズマ窒化膜17を成長さ
せ、このプラズマ窒化膜17を平行平板型ドライエッチン
グ法でエッチング除去することにより開孔側壁にのみプ
ラズマ窒化膜17を残すことができる。An improvement of the structure of the semiconductor device shown in FIG. 5 is that of the structure shown in FIG. 6, in which a plasma nitride film 17 is formed on the side of the passivation film on the bonding pad 13.
Is provided. As a manufacturing method, after the structure shown in FIG. 5 is obtained, a plasma nitride film 17 is further grown, and this plasma nitride film 17 is etched and removed by a parallel plate type dry etching method so that only the side wall of the opening is formed. The plasma nitride film 17 can be left.
上述した従来の半導体装置におけるパッシベーション
膜では、第６図に示したように、ボンディングパッド13
上のパッシベーション膜の側面にプラズマ窒化膜17が存
在するため、半導体装置の信頼性は多少向上している。
しかし、プラズマ窒化膜17の形成は制御が難しい。特
に、側面に残すプラズマ窒化膜17の膜厚を精度よく再現
させるのは、大きな困難を伴う。側面のプラズマ窒化膜
17の膜厚が薄くなると、水分は容易に塗布・焼成膜15側
へ浸入し、ひいては容易に半導体内部にまで水分が浸入
し、半導体装置の劣化を防ぐことが極めて困難になると
いう欠点がある。In the above-described passivation film in the conventional semiconductor device, as shown in FIG.
Since the plasma nitride film 17 exists on the side surface of the upper passivation film, the reliability of the semiconductor device is somewhat improved.
However, the formation of the plasma nitride film 17 is difficult to control. Particularly, it is very difficult to accurately reproduce the thickness of the plasma nitride film 17 left on the side surface. Side plasma nitride film
When the film thickness of 17 becomes thin, there is a drawback that moisture easily penetrates into the coating / firing film 15 side, and thus easily penetrates into the inside of the semiconductor, and it becomes extremely difficult to prevent deterioration of the semiconductor device. .
本発明の半導体装置は、半導体基板上に絶縁膜を介し
て形成されたボンディングパッドと、前記ボンディング
パッド上の周辺部に形成されたシリコンを主成分とする
溶液を塗布・焼成した第１の絶縁膜と気相成長法により
形成した第２の絶縁膜からなるパッシベーション膜と、
前記ボンディングパッド上の前記パッシベーション膜の
側面に形成された気相成長法による第３の絶膜膜とを有
する半導体装置において、前記パッシベーション膜の側
面における前記第１の絶縁膜は前記第２の絶縁膜に対し
てアンダーカット部を有するものである。A semiconductor device according to the present invention includes a bonding pad formed on a semiconductor substrate via an insulating film, and a first insulating material formed by coating and firing a solution containing silicon as a main component formed on a peripheral portion of the bonding pad. A passivation film comprising a film and a second insulating film formed by a vapor deposition method;
A third insulating film formed by a vapor deposition method on a side surface of the passivation film on the bonding pad, wherein the first insulating film on the side surface of the passivation film is the second insulating film. The film has an undercut portion.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の製造方法を説明する
ための半導体チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip for explaining a manufacturing method according to a first embodiment of the present invention.
まず、第１図（ａ）に示す如く、シリコン基板11上に
酸化シリコン膜12を形成し、膜厚１μｍのアルミ配線に
接続するボンディングパッド13を形成する。次に、パッ
シベーション膜として、厚さ5000Åのプラズマ窒化膜14
Aと厚さ2000Åのシリコンを主成分とする塗布・焼成膜1
5と、厚さ5000のプラズマ窒化膜14Bとを形成する。次
に、ボンディングパッド13の部分を平行平板型ドライエ
ッチング法を用いて開孔する。First, as shown in FIG. 1A, a silicon oxide film 12 is formed on a silicon substrate 11, and a bonding pad 13 connected to an aluminum wiring having a thickness of 1 μm is formed. Next, as a passivation film, a plasma nitride film 14
A and 2,000mm thick silicon-based coating / firing film 1
5 and a 5000-nm-thick plasma nitride film 14B are formed. Next, a portion of the bonding pad 13 is opened using a parallel plate type dry etching method.
次に、希釈フッ化水素酸で塗布・焼成膜15を１μｍエ
ッチングする。このとき、プラズマ窒化膜14A,14Bは殆
どエッチングされないので、開孔部側面形状は塗布・焼
成膜15の部分だけが１μｍ後退しアンダーカット部16が
形成される。この状態で全面に再度プラズマ窒化膜17を
6000Åの厚さに形成する。プラズマ窒化膜はカバレッジ
が良いので、アンダーカッド部16にも十分な膜厚のプラ
ズマ窒化膜が形成される。Next, the coating and firing film 15 is etched by 1 μm with diluted hydrofluoric acid. At this time, since the plasma nitride films 14A and 14B are hardly etched, only the coating / firing film 15 is recessed by 1 μm in the side surface of the opening, and the undercut portion 16 is formed. In this state, a plasma nitride film 17 is again formed on the entire surface.
Formed to a thickness of 6000 mm. Since the plasma nitride film has good coverage, a sufficient thickness of the plasma nitride film is also formed on the under-quad portion 16.
この状態で平行平板型ドライエッチング法でプラズマ
窒化膜17を異方性エッチングすると、第１図（ｂ）に示
す如く、プラズマ窒化膜17がパッシベーション膜の側面
に残る。When the plasma nitride film 17 is anisotropically etched by the parallel plate dry etching method in this state, the plasma nitride film 17 remains on the side surface of the passivation film as shown in FIG.
このように構成された第１の実施例によれば、塗布・
焼成膜15は十分に厚いプラズマ窒化膜17で側面部を保護
されているので、水分の浸入に対して極めて強い構造の
半導体装置が得られ信頼性は向上する。According to the first embodiment configured as described above,
Since the fired film 15 is protected on the side surface by the sufficiently thick plasma nitride film 17, a semiconductor device having a structure that is extremely resistant to intrusion of moisture is obtained, and the reliability is improved.
更に本第１の実施例によれば、第１の実施例と同等の
信頼性を得るための、例えば金属配線形成の如き高価な
プロセスを用いる必要がないので、コストが安く、製造
の納期短縮化，プロセスの容易さ故の製造良品率の向上
などを図ることができる。Further, according to the first embodiment, it is not necessary to use an expensive process such as the formation of a metal wiring to obtain the same reliability as that of the first embodiment. It is possible to improve the ratio of non-defective products due to simplification and easy process.
第７図は、従来構造の半導体装置と、本発明の実施例
の信頼性試験をシリコンウェーハ状態で行った結果を示
す図である。試験環境は、125℃、温度100％,2.2気圧の
条件で行った。不良率の判定は、ボンディングパッドか
ら100μｍ離れた場所でのアルミ配線の腐蝕の有無で行
った。FIG. 7 is a diagram showing the results of reliability tests of a semiconductor device having a conventional structure and an embodiment of the present invention performed in a silicon wafer state. The test was conducted under the conditions of 125 ° C., 100% temperature, and 2.2 atm. The defect rate was determined based on the presence or absence of corrosion of the aluminum wiring at a location 100 μm away from the bonding pad.
第５図に示した従来例では、12時間以内に不良が発生
し、24時間後にはほぼ全数不良となった。改善された従
来技術である第６図に示した従来例では、ほぼ100％不
良になるまでに約60時間を要している。しかし、ここで
特徴的なことは、試験の初期段階で約10％の不良が既に
発生していることである。これは、第６図に示したプラ
ズマ窒化膜17の制御が困難であり、部分的に薄いところ
が出来、そこから水分が浸入したためと考えられる。In the conventional example shown in FIG. 5, a failure occurred within 12 hours, and almost all failures occurred after 24 hours. In the prior art example shown in FIG. 6, which is an improved prior art, it takes about 60 hours to become almost 100% defective. However, what is characteristic here is that about 10% of defects have already occurred in the initial stage of the test. This is probably because the control of the plasma nitride film 17 shown in FIG. 6 was difficult, and a thin portion was formed, from which water entered.
それに反し、第１の実施例では48時間まで不良がまっ
たくなく、顕著な改善が示されている。プラスチック樹
脂等で保護されると、耐湿性は格段に向上するので、第
１図の構造であれば十分な耐湿性を有すると言える。On the contrary, the first example shows no remarkable defects up to 48 hours and a remarkable improvement. When protected by a plastic resin or the like, the moisture resistance is significantly improved, and therefore it can be said that the structure shown in FIG. 1 has sufficient moisture resistance.
第２図は本発明の第２の実施例の断面図である。シリ
コン基板11上には酸化シリコン膜12を介してアルミ配線
に接続するボンディングパッド13が形成されている。そ
して、このボンディングパッド13の周辺部には、ボンデ
ィングパッド13を陽極化成して形成されたアルミナ膜24
が形成されており、更にパッシベーション膜としてアン
ダーカット部16を有する塗布・焼成膜15の第１の絶縁膜
とプラズマ窒化膜14の第２の絶縁膜とが形成されてい
る。更にボンディングパッド13上のパッシベーション膜
の側面には第３の絶縁膜としてプラズマ窒化膜17が形成
されている。FIG. 2 is a sectional view of a second embodiment of the present invention. On a silicon substrate 11, a bonding pad 13 connected to an aluminum wiring via a silicon oxide film 12 is formed. An alumina film 24 formed by anodizing the bonding pad 13 is formed around the bonding pad 13.
Are formed, and a first insulating film of a coating / baking film 15 having an undercut portion 16 as a passivation film and a second insulating film of a plasma nitride film 14 are formed. Further, on the side surface of the passivation film on the bonding pad 13, a plasma nitride film 17 is formed as a third insulating film.
このように構成された第２の実施例によれば、ボンデ
ィングパッド13を構成するAl膜がアルミナ膜24により覆
われているため、窒化シリコン膜で直接覆われる場合に
比べ、耐湿性が向上すると共に、ストレスマイグレーシ
ョンによるAl消失の発生が極めて少くなるという利点が
ある。According to the second embodiment thus configured, since the Al film forming the bonding pad 13 is covered with the alumina film 24, the moisture resistance is improved as compared with the case where the Al film is directly covered with the silicon nitride film. In addition, there is an advantage that the occurrence of Al loss due to stress migration is extremely reduced.
なお、塗布・焼成膜の性質にもよるが、アルミナ膜24
を無くし、塗布・焼成膜15を直接ボンディングパッド13
に接触させることも可能である。Note that, depending on the properties of the coating / baking film, the alumina film 24
And apply and bake film 15 directly to bonding pad 13
It is also possible to make contact.
更に、上記実施例においてはパッシベーション膜とし
てプラズマ窒化膜を用いた場合について説明したが、酸
化膜，オキシナイトライド膜，リンケイ酸ガラスなど目
的に応じた組合わせを用いることができる。Further, in the above embodiment, the case where the plasma nitride film is used as the passivation film has been described, but a combination according to the purpose, such as an oxide film, an oxynitride film, and phosphosilicate glass, can be used.
以上説明したように本発明は、ボンディングパッド上
の周辺部に形成する塗布・焼成膜からなる第１の絶縁膜
と気相成長法による第２の絶縁膜からなるパッシベーシ
ョン膜のうち、第１の絶縁膜にアンダーカット部を設け
ることにより、パッシベーション膜の側面に形成される
気相成長による第３の絶縁膜がこのアンダーカット部に
も形成されるため、半導体装置の耐水性が向上するとい
う効果がある。従って、信頼性の高い半導体装置を得る
ことができる。As described above, according to the present invention, the first insulating film formed of a coating / baked film formed in the peripheral portion on the bonding pad and the first insulating film formed of the second insulating film formed by the vapor deposition method are used. By providing the undercut portion in the insulating film, the third insulating film formed by vapor phase growth formed on the side surface of the passivation film is also formed in the undercut portion, so that the water resistance of the semiconductor device is improved. There is. Therefore, a highly reliable semiconductor device can be obtained.
第１図及び第２図は本発明の第１及び第２の実施例の断
面図、第３図〜第６図は従来例を説明するための半導体
チップの断面図、第７図は耐湿性試験結果を示す図であ
る。 11……シリコン基板、12……酸化シリコン膜、13……ボ
ンディングパッド、14,14A,14B……プラズマ窒化膜、15
……塗布・焼成膜、16……アンダーカット部、17……プ
ラズマ窒化膜、23……アルミ配線、24……アルミナ膜。1 and 2 are cross-sectional views of the first and second embodiments of the present invention, FIGS. 3 to 6 are cross-sectional views of a semiconductor chip for explaining a conventional example, and FIG. 7 is moisture resistance. It is a figure showing a test result. 11 ... silicon substrate, 12 ... silicon oxide film, 13 ... bonding pad, 14, 14A, 14B ... plasma nitride film, 15
…… Coated and fired film, 16 …… Undercut part, 17 …… Plasma nitride film, 23 …… Aluminum wiring, 24 …… Alumina film.
Claims (1)
ボンディングパッドと、前記ボンディングパッド上の周
辺部に形成されたシリコンを主成分とする溶液を塗布・
焼成した第１の絶縁膜と気相成長法により形成した第２
の絶縁膜からなるパッシベーション膜と、前記ボンディ
ングパッド上の前記パッシベーション膜の側面に形成さ
れた気相成長法による第３の絶縁膜とを有する半導体装
置において、 前記パッシベーション膜の側面における前記第１の絶縁
膜は前記第２の絶縁膜に対してアンダーカット部を有す
ることを特徴とする半導体装置。A method of applying a bonding pad formed on a semiconductor substrate via an insulating film and a solution containing silicon as a main component formed on a peripheral portion of the bonding pad.
The fired first insulating film and the second insulating film formed by the vapor deposition method
A semiconductor device having a passivation film made of an insulating film of the following, and a third insulating film formed by vapor deposition on a side surface of the passivation film on the bonding pad; A semiconductor device, wherein the insulating film has an undercut portion with respect to the second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63311204A JP2751274B2 (en) | 1988-12-09 | 1988-12-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63311204A JP2751274B2 (en) | 1988-12-09 | 1988-12-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02156640A JPH02156640A (en) | 1990-06-15 |
| JP2751274B2 true JP2751274B2 (en) | 1998-05-18 |
Family
ID=18014356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63311204A Expired - Lifetime JP2751274B2 (en) | 1988-12-09 | 1988-12-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2751274B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100702120B1 (en) * | 2001-06-30 | 2007-03-30 | 주식회사 하이닉스반도체 | Bonding PAD of semiconductor device and method for forming the same |
| KR100869112B1 (en) * | 2002-01-14 | 2008-11-17 | 삼성전자주식회사 | Reflective type liquid crystal display device and method of manufacturing the same |
-
1988
- 1988-12-09 JP JP63311204A patent/JP2751274B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02156640A (en) | 1990-06-15 |
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