JPH03218630A - Semiconductor device having high breakdown strength - Google Patents
Semiconductor device having high breakdown strengthInfo
- Publication number
- JPH03218630A JPH03218630A JP1397490A JP1397490A JPH03218630A JP H03218630 A JPH03218630 A JP H03218630A JP 1397490 A JP1397490 A JP 1397490A JP 1397490 A JP1397490 A JP 1397490A JP H03218630 A JPH03218630 A JP H03218630A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide film
- layer
- semiconductor device
- film
- polyimide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 230000015556 catabolic process Effects 0.000 title claims abstract description 4
- 229920001721 polyimide Polymers 0.000 claims abstract description 31
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 18
- 230000002093 peripheral effect Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 abstract description 4
- 238000004140 cleaning Methods 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract description 2
- 230000000087 stabilizing effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 3
- 239000004642 Polyimide Substances 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 230000002708 enhancing effect Effects 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ポリイミド膜を表面保護膜として用いる高耐
圧半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a high voltage semiconductor device using a polyimide film as a surface protection film.
［従来の技術］
高耐圧半導体装置の一構造としてガードリング構造があ
る。第２図及び第３図はかかる半導体装置の基本構成を
示すものである。[Prior Art] A guard ring structure is one structure of a high voltage semiconductor device. FIGS. 2 and 3 show the basic structure of such a semiconductor device.
第２図は全体図を示すもので、活性領域部Ａとガードリ
ング部（ＥＱＲ部含む）Ｂから成り、第３図は前記ガー
ドリング部ＢにおけるＥＱＲ部分から半導体装置周辺に
かけての断面図で、半導体基板ｌ、熱酸化膜２、ＣＶＤ
酸化膜３、ＥＱＲ部（１！）４、ポリイミド膜５、スク
ライブレーン７より成る。また、周辺部は熱酸化膜２、
ＣＶＤ酸化膜３、ポリイミド膜５とも端部は揃えている
が、ポリイミド膜５が熱酸化膜２とＣＶＤ酸化膜３を覆
うようにスクライブレーン７側に張り出している。FIG. 2 shows an overall view, consisting of an active region part A and a guard ring part (including an EQR part) B, and FIG. 3 is a cross-sectional view of the guard ring part B from the EQR part to the periphery of the semiconductor device. Semiconductor substrate 1, thermal oxide film 2, CVD
It consists of an oxide film 3, an EQR section (1!) 4, a polyimide film 5, and a scribe lane 7. In addition, the peripheral area has a thermal oxide film 2,
Although the ends of the CVD oxide film 3 and the polyimide film 5 are aligned, the polyimide film 5 protrudes toward the scribe lane 7 side so as to cover the thermal oxide film 2 and the CVD oxide film 3.
［発明が解決しようとする課Ｂ］
ところで、前述の如き半導体装置においては、ポリイミ
ド膜５と下地、例えばシリコン基板１やシリコン酸化膜
２との密着性に問題があり、次工程で、例えばフッ酸系
の薬品処理を行った場合、薬液がポリイミド膜５と下地
の間に侵入し、ポリイミド膜５自体の剥離を生じ、信顧
性を悪化させるという問題があった。[Problem B to be Solved by the Invention] By the way, in the semiconductor device as described above, there is a problem in the adhesion between the polyimide film 5 and the underlying layer, such as the silicon substrate 1 or the silicon oxide film 2. When acid-based chemical treatment is performed, there is a problem in that the chemical solution enters between the polyimide film 5 and the underlying layer, causing peeling of the polyimide film 5 itself and deteriorating reliability.
本発明は、上記問題点に鑑みなされたもので、その目的
とするところは、信顛性の高い高耐圧半導体装置を提供
するにある。The present invention has been made in view of the above problems, and its object is to provide a highly reliable high voltage semiconductor device.
［課題を解決するための手段］
前記課題を解決するため本発明は、表面保護膜にポリイ
ミド膜を用いた高耐圧の半導体装置において、素子周辺
部（スクライブレーン部分）にポリイミド膜と密着性の
良いアルミ（Ａ１）の層を設けるとともに、前記ポリイ
ミド膜を形成する際に、ポリイミド膜の端部を前記アル
ミ層の最外側端部若しくはアルミ層を覆うように形成し
たことを特徴とするものである。[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a high-voltage semiconductor device using a polyimide film as a surface protection film, in which a polyimide film and an adhesive layer are formed around the device periphery (scribe lane portion). In addition to providing a layer of high quality aluminum (A1), when forming the polyimide film, the edge of the polyimide film is formed to cover the outermost end of the aluminum layer or the aluminum layer. be.
［作 用］
上記のように、素子周辺部（スクライブレーン部分）に
ポリイミド膜と密着性の良いアルミ層を設け、ポリイミ
ド膜をアルミ層と接するように形成したことにより、ポ
リイミド膜と下地との密着性が向上し、半導体装置の信
顛性を高めることができる。[Function] As mentioned above, by providing an aluminum layer with good adhesion to the polyimide film around the device periphery (scribe lane part) and forming the polyimide film in contact with the aluminum layer, the contact between the polyimide film and the underlying layer is improved. Adhesion is improved, and reliability of the semiconductor device can be improved.
［実施例］
第１図は本発明の一実施例を示すもので、半導体装置の
周辺部（スクライブレーン部分）の断面を示すものであ
る。[Embodiment] FIG. 1 shows an embodiment of the present invention, and shows a cross section of a peripheral portion (scribe lane portion) of a semiconductor device.
この半導体装置は、半導体基板ｌの表面に高耐圧安定化
のためのＥＱＲ部（／ｌ）４を設けており、同時にスク
ライブレーン７側に張り出したアルミ層６を設け、その
上に表面保護膜としてＣ■Ｄ酸化膜３、ポリイミド膜５
を設けている。This semiconductor device is provided with an EQR section (/l) 4 for stabilizing high breakdown voltage on the surface of a semiconductor substrate l, and at the same time an aluminum layer 6 extending toward the scribe lane 7 side is provided, and a surface protective film is provided on the aluminum layer 6. As C■D oxide film 3, polyimide film 5
has been established.
このように構成された半導体装置では、周辺部（スクラ
イブレーン部分）７においてポリイミド膜５とアルミ層
６が接するので、周辺部７におけるポリイミド膜５と下
地との密着性が向上し、外的要因、例えば水分等の侵入
を防ぐとともに、次工程での薬液（例えばフッ酸）洗浄
に対するマスキング効果も高くなり、半導体装置の信頼
性を高くすることができる。In the semiconductor device configured in this manner, the polyimide film 5 and the aluminum layer 6 are in contact with each other in the peripheral area (scribe lane area) 7, so that the adhesion between the polyimide film 5 and the underlying layer in the peripheral area 7 is improved, and external factors In addition to preventing the intrusion of, for example, moisture, the masking effect against cleaning with a chemical solution (eg, hydrofluoric acid) in the next step is also enhanced, and the reliability of the semiconductor device can be increased.
なお、本発明は上記実施例に限定されるものではなく、
ポリイミド膜がスクライブレーン部分のアルミを全て覆
う構成でもよく、また、電極材料もアルミに限らず、ア
ルミ・シリコン等、ポリイミド膜と密着性の良い材料な
らよい。さらに、ガードリング構造以外の高耐圧構造で
もよい。Note that the present invention is not limited to the above embodiments,
The polyimide film may cover all of the aluminum in the scribe lane portion, and the electrode material is not limited to aluminum, but may be any material that has good adhesion to the polyimide film, such as aluminum or silicon. Furthermore, a high-voltage structure other than the guard ring structure may be used.
［発明の効果］
本発明は上記のように、半導体装置の周辺部にポリイミ
ド膜と密着性の良いアルミ層を設け、ポリイミド膜をア
ルミ層と接するか又は覆うように構成したことにより、
ポリイミド膜と下地との密着性が向上し、信鎖性を高い
半導体装置を提供することができた。[Effects of the Invention] As described above, the present invention provides the aluminum layer with good adhesion to the polyimide film in the peripheral part of the semiconductor device, and the polyimide film is configured to contact or cover the aluminum layer.
The adhesion between the polyimide film and the underlying layer was improved, making it possible to provide a semiconductor device with high reliability.
第１図は本発明の一実施例を示す要部断面図、第２図及
び第３図は従来例を示す断面図で、第２図は全体を示し
、第３図は素子周辺部を示す。
１・・・半導体基板、２・・・悲酸化膜、３・・・ＣＶ
Ｄ酸化膜、４・・・ＥＱＲ部、５・・・ポリイミド膜、
６・・・アルミ層、７・・・スクライブレーン。Fig. 1 is a sectional view of a main part showing an embodiment of the present invention, Figs. 2 and 3 are sectional views showing a conventional example, Fig. 2 shows the whole, and Fig. 3 shows the peripheral part of the element. . 1... Semiconductor substrate, 2... Sad oxide film, 3... CV
D oxide film, 4... EQR part, 5... polyimide film,
6...Aluminum layer, 7...Scribe lane.
Claims (1)
体装置において、素子周辺部（スクライブレーン部分）
にアルミ（Ａｌ）の層を設けるとともに、前記ポリイミ
ド膜の端部を前記アルミ層の最外側端部若しくはアルミ
層を覆うように形成したことを特徴とする高耐圧半導体
装置。(1) In a high-voltage semiconductor device using a polyimide film as a surface protection film, the peripheral area of the element (scribe lane area)
1. A high breakdown voltage semiconductor device, characterized in that an aluminum (Al) layer is provided on the substrate, and an end of the polyimide film is formed to cover the outermost end of the aluminum layer or the aluminum layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1397490A JPH03218630A (en) | 1990-01-24 | 1990-01-24 | Semiconductor device having high breakdown strength |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1397490A JPH03218630A (en) | 1990-01-24 | 1990-01-24 | Semiconductor device having high breakdown strength |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03218630A true JPH03218630A (en) | 1991-09-26 |
Family
ID=11848198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1397490A Pending JPH03218630A (en) | 1990-01-24 | 1990-01-24 | Semiconductor device having high breakdown strength |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03218630A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0613778A2 (en) * | 1993-03-01 | 1994-09-07 | SCITEX DIGITAL PRINTING, Inc. | Passivation layer for ceramic based charge plates |
| US7970605B2 (en) | 2005-01-12 | 2011-06-28 | Nippon Telegraph And Telephone Corporation | Method, apparatus, program and recording medium for long-term prediction coding and long-term prediction decoding |
-
1990
- 1990-01-24 JP JP1397490A patent/JPH03218630A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0613778A2 (en) * | 1993-03-01 | 1994-09-07 | SCITEX DIGITAL PRINTING, Inc. | Passivation layer for ceramic based charge plates |
| EP0613778A3 (en) * | 1993-03-01 | 1995-04-05 | Scitex Digital Printing Inc | Passivation layer for ceramic based charge plates. |
| US7970605B2 (en) | 2005-01-12 | 2011-06-28 | Nippon Telegraph And Telephone Corporation | Method, apparatus, program and recording medium for long-term prediction coding and long-term prediction decoding |
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