JPS61100952A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61100952A
JPS61100952A JP59222446A JP22244684A JPS61100952A JP S61100952 A JPS61100952 A JP S61100952A JP 59222446 A JP59222446 A JP 59222446A JP 22244684 A JP22244684 A JP 22244684A JP S61100952 A JPS61100952 A JP S61100952A
Authority
JP
Japan
Prior art keywords
layer
protective film
insulating protective
melting point
high melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59222446A
Other languages
Japanese (ja)
Inventor
Takashi Mizuguchi
隆史 水口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP59222446A priority Critical patent/JPS61100952A/en
Publication of JPS61100952A publication Critical patent/JPS61100952A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To improve adhesive properties with an insulating protective film to protect a metallic layer as a lower layer, and to prevent the deterioration of characteristics of an element by forming a metallic thin-layer, which is easy to be oxidized and has the high melting point, between Ag or a compound layer of Ag attached onto the surface of the element and the insulating protective film. CONSTITUTION:When Ag or a compound 9 of Ag and another metal is affixed onto an element surface and wired and connected and an insulating protective film 17 is applied, a metallic thin-layer 16, which is easy to be oxidized and has the high melting point, is shaped between Ag or the compound layer 9 of Ag and another metal and the insulating protective film 17. Since adhesive properties and affinity with the Si3N4 film 17, etc. are improved and heat resistance and corrosion resistance must also be increased sufficiently as the quality of materials of the metallic thin-layer 16, a titanium group, such as Ti, Zr, Hf, etc., a vanadium group, such as V, Nb, etc. or a metal, which is easy to be oxidized but has the high melting point, such as Cr, Mo, W, etc. is employed.

Description

【発明の詳細な説明】 産業上の利用分野 この発明は、半導体装置の素子表面に形成する金属層の
処理に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to processing of a metal layer formed on the surface of a semiconductor device.

従来の技術 従来より周知の通り、定電圧ダイオードは、ＰＮ接合の
空乏層に量子力学的トンネル効果による降伏現象を起さ
せる、ツエーナダイオードがある。2. Description of the Related Art As is well known in the art, a Zener diode is a constant voltage diode that causes a breakdown phenomenon in a depletion layer of a PN junction due to a quantum mechanical tunnel effect.

しかしツエーナダイオードは、温度上昇が起しがちで、
ノイズも発生する欠点がある。そこで上述のツエーナダ
イオードに替って、欠点を是正する定電圧素子として、
次に示すパンチスルー型定電圧素子がある。However, Zener diodes are prone to temperature rise,
It also has the disadvantage of generating noise. Therefore, in place of the above-mentioned Zener diode, as a constant voltage element to correct the drawbacks,
There is a punch-through type constant voltage element shown below.

すなわち、バンチスルー予定電圧素子は、第４図に示す
ように、２４層ｌ上にＰＦｍ２を形成し、さらにｒＸ層
３、Ｐ＋層４を選択拡散させ、ＰｎＰサントイ・ツチ形
三層構造としたものである。この素子は、１層３０ペー
ス幅Ｗを数μｍ程度と薄くシ、かつｒｌｊｌ　Ｂの濃度
を低くして比抵抗を高く設定して、Ｐ＋層ｌ及び７層２
を正、Ｐ＋層４を負にパイアスした時に、逆バイアスさ
れるｐ＋ｎ接合５近涛の空乏層６を、０層３内で脹れさ
せて、正バイアスのｐｒｒ接合７の空乏ｍ８へ面突させ
るバンナスルー現療を利用したものである。さらに、こ
の１子は、ｖＰ・特性を向上させて実用性を良好とする
ために、Ｐｎ接合７０表面（至）に露出している終端７
′は、Ａｇ＋ＡｕＡｇ或いはＮ１Ａｐなどの金属層９で
短絡させている。また、この種素子は、例えば、特公昭
６Ｂ−２７６５２号公報に示されているように、第５図
で筒状ガヲスパ〜ブ１０内に素子１１を入れて、両開口
からピストン状のスフブリード１２．１２を挾み付けし
て、加熱封止するのが一般的である。そこで、Ｐ”４４
にはＡｇメ１．、キにてバンプ環１ｉ１３を形成し、挾
み付けによるＰ”ｎ接合５やＰｎ接合７の破損防止を図
っている。That is, as shown in FIG. 4, the bunch-through voltage element has a PnP Santoi-Tsuchi type three-layer structure by forming PFm2 on the 24 layers, and selectively diffusing the rX layer 3 and the P+ layer 4. It is something. This element has a thin layer width W of 30 layers of about several μm, a low concentration of rljl B and a high specific resistance, and a P+ layer l and 7 layers 2
When P+ layer 4 is biased positively and P+ layer 4 is biased negatively, the depletion layer 6 near the reverse biased p+n junction 5 swells in the 0 layer 3 and protrudes into the depletion m8 of the positively biased prr junction 7. This is a method that utilizes the current medical treatment. Furthermore, in order to improve the vP characteristics and improve the practicality, the terminal 7 is exposed on the surface of the Pn junction 70.
' is short-circuited by a metal layer 9 such as Ag+AuAg or N1Ap. In addition, this type of element is disclosed, for example, in Japanese Patent Publication No. 6B-27652, as shown in FIG. .12 is sandwiched and heat sealed. Therefore, P”44
Agme 1. , a bump ring 1i13 is formed in order to prevent damage to the P''n junction 5 and the Pn junction 7 due to clamping.

発明が解決しようとする問題点 七ころで、上述したバンチスルー型室電圧素子を形成す
る場合には、第４図に示した金属層９を残しかつバンプ
［極１３をＡｇメフキするには、紡・縁保護％ｊｌ１４
’を被りさせてカバーする必要がある。しかしながら、
金属層９上には、一般にＳＩＯ。Problems to be Solved by the Invention When forming the above-mentioned bunch-through type chamber voltage element, it is necessary to leave the metal layer 9 shown in FIG. Spinning/edge protection%jl14
'It is necessary to cover it by putting it on. however,
On the metal layer 9, there is generally an SIO.

等の絶縁保護ＩＪｊＪ１４’を、十分に密着性を持たせ
て被覆することが困難である。そこで金１！！！層９を
５１０１等と親和性がよい金属に変更しようとすれば、
加熱封止時のａｔτの影響を受けてしまい、やはり密着
性が堝われる危険が大であった。It is difficult to cover the insulation protection IJjJ14' with sufficient adhesion. So gold 1! ! ! If you try to change layer 9 to a metal that has good affinity with 5101 etc.,
It was affected by atτ during heat sealing, and there was a great risk that the adhesion would deteriorate.

この発明は、上記事情に鑑み提案されたものである。This invention was proposed in view of the above circumstances.

問題点を解決するための手段 この発明はＡｇ若１．＜はＡｇと他の金属との化合物を
、素子表面に付着させて配線・接続し、さらに絶縁保護
膜を？！１覆させるものにおいて、前述のＡｔ若しくは
Ａｇと他の金属との化合物層と、絶縁保護膜との間に、
酸化し易すくかり高融点の金属薄層を設けることを特徴
としている。すなわち、この発明は、ＡｇやＡｇと他の
金属層に８１０゜膜等を付着させる際に、ｈａ薄層が下
地層となるものである。Means for Solving the Problems This invention is based on Ag Young 1. < is a compound of Ag and other metals attached to the element surface for wiring/connection, and then an insulating protective film? ! 1, between the above-mentioned compound layer of At or Ag and another metal and the insulating protective film,
It is characterized by providing a thin metal layer that is easily oxidized and has a high melting point. That is, in this invention, when an 810° film or the like is attached to Ag or other metal layers, the ha thin layer serves as a base layer.

作用 この発明は、金属薄層を設けることにより、付着した金
属薄層の絶縁保護膜を形成させる上面が、直ちにａ化し
好適な粗い微小凹凸面となるので、絶縁保護°膜との密
着性が著しく良くなる。さらにこの発明は、金属！１７
層が配線・接読金属層と絶縁膜Ｆ［との中間に介在する
ので、素子表面のニーＶチングや、完成した素子の加熱
封止作業等において、下層にある金属層を保護する皮殻
となり、素子の特性劣化をも防ぐことができる。Function: By providing a thin metal layer, the upper surface of the deposited thin metal layer on which the insulating protective film is formed immediately becomes a and becomes a suitable rough and minute uneven surface, so that the adhesion with the insulating protective film is improved. It gets noticeably better. Moreover, this invention uses metal! 17
Since the layer is interposed between the wiring/reading metal layer and the insulating film F[, it is a shell that protects the underlying metal layer during knee V-etching of the element surface, heat sealing of the completed element, etc. Therefore, it is possible to prevent deterioration of the characteristics of the element.

実施例 第１図は、この発明の一実施例を示すパンチスルー型定
電圧素子の断面図で、従来の場合を示した第４図と同一
図番のものは、同一呼称であり、重１夏説明を避けた。Embodiment FIG. 1 is a sectional view of a punch-through type constant voltage element showing an embodiment of the present invention. Figures with the same numbers as those in FIG. Summer avoided explanation.

そして、１４は素子表面のバンプ環［１３及びＰＮ接合
短絡金属層９以外を覆っているＳ１０．絶縁膜である。14 is a bump ring on the element surface [S10. It is an insulating film.

さらに、１５は、素子裏面のＰ＋層１上に全面被着され
たＡｔ電極である。さて、１６は、この発明の主旨とな
る金属薄層で、円Ｃ部を拡大して示す第２図のように、
ｐｎ　接合短絡金属層９上の全面に、真空蒸着或いはス
パ、１．タリングにより、Ｔ１を約２００〜ｔｏｏ。Furthermore, 15 is an At electrode entirely deposited on the P+ layer 1 on the back side of the element. Now, 16 is a metal thin layer which is the gist of this invention, as shown in Fig. 2, which shows an enlarged view of circle C.
Vacuum evaporation or spa treatment is performed on the entire surface of the pn junction shorting metal layer 9.1. By taring, T1 is about 200~too.

Ａ程の膜厚に付着させたものである。そして１７は、金
属４層１６上から周縁ｏｓｔｏ＊絶＆ｔ＃１４上へかけ
て、ＣＶＤ法により形成したｓｌ、Ｎ４膜である。The film was deposited to a thickness of about A. Reference numeral 17 denotes an SL, N4 film formed by the CVD method from the top of the metal 4 layer 16 to the peripheral osto * insulation &t #14.

ここで、金属薄層１６の材質は重要で、Ｓ　ｉ、　ＩＪ
。Here, the material of the metal thin layer 16 is important, and S i, IJ
.

嘆１７との密着性０ｍ和性が良好であり、しかも耐熱、
耐ｆｆｉ性も十分なものとする必要があるので、Ｔ１以
外にＺｒ％Ｉ（ｆ等のチタン族、Ｖ、Ｎ１）１４のバナ
ジウム族、あるいは、Ｃｒ、ＭＯｏｔ等のσ化し易すい
か高融点の金属が適切である。It has good adhesion and compatibility with 17, and is also heat resistant.
Since it is necessary to have sufficient ffi resistance, in addition to T1, Zr%I (titanium group such as f, V, N1), vanadium group of 14, or water or high melting point material that is easily converted to sigma such as Cr, MOot etc. Metal is suitable.

以上の実施例は、Ｐｎ接合を二つ設けたＰｎＰ三層構造
の単体素子の場合を示したが、この発明は、この場合に
限定するものではなく、例えば第８因に示すように、Ｘ
Ｃ素子の一部にＰａＰ溝造の素子１８とＰｎＩ５ｊＮ造
の素子１９とを埋め込み形成し、ＡＰ　、ＴｉＡｐ　、
ＡｕＡｇ、Ｎ１Ａｇ等の金属＆！線パターン９′で接続
し、金属薄層１６’及び絶縁保護膜１７’を形成するも
のにも適用することができる。Although the above embodiments have shown the case of a single element having a PnP three-layer structure in which two Pn junctions are provided, the present invention is not limited to this case. For example, as shown in the eighth factor,
An element 18 having a PaP groove structure and an element 19 having a PnI5jN structure are embedded in a part of the C element, and AP, TiAp,
Metals such as AuAg and N1Ag &! It can also be applied to a structure in which a thin metal layer 16' and an insulating protective film 17' are formed by connecting with a line pattern 9'.

発明の効果 この発明によれば、素子表面に設ける金属層とこの上に
設ける絶縁保ｇＨとが、中間に介在させる金Ｗｔ薄層に
より、十分強固に密着できるので、他のＷ、係形成や製
造プロセスで工・１チングや完成欝子の封止作業におけ
る素子の汚損や破損並びに特性劣化を防げることになり
、量産性を低下させることなく、信頼性を向上させ得る
優れた効果がある。Effects of the Invention According to the present invention, the metal layer provided on the surface of the element and the insulating layer GH provided thereon can be firmly adhered to each other by the thin gold Wt layer interposed between them, thereby preventing the formation of other W, bonding, etc. This prevents contamination, damage, and characteristic deterioration of the element during machining and sealing of the completed cylinder during the manufacturing process, and has the excellent effect of improving reliability without reducing mass productivity.

・）・)

【図面の簡単な説明】[Brief explanation of the drawing]

＠１図は、この発明の一実施例を示す半導体素子の断面
図、＄２図は、その円Ｃ部を拡大して示す要部断面図、
第３図は、その池の実施例を示す半導体素子の断面図、
＠４図は、従来の（この発明以前の）半導体素子の断面
図、第５図は、その封止完了した半導体装置°の断面図
である。 ９．９′・・・・・・金″！Ｘ層、　　１６．１６’・
・・・・・渣１薄層、１７．１７’・・・・・・絶１１
保護膜。 ・−、ノFigure @1 is a cross-sectional view of a semiconductor element showing an embodiment of the present invention, Figure $2 is a cross-sectional view of a main part showing an enlarged circle C section,
FIG. 3 is a cross-sectional view of a semiconductor device showing an embodiment of the pond;
Figure 4 is a cross-sectional view of a conventional semiconductor element (prior to this invention), and Figure 5 is a cross-sectional view of the semiconductor device after its sealing is completed. 9.9'...Gold''!X layer, 16.16'・
...Residue 1 thin layer, 17.17' ... Absolute 11
Protective film.・－、ノ

Claims (2)

【特許請求の範囲】[Claims] 　（１）Ａｇ若しくはＡｇと他の金属との化合物を、素
子表面に付着させて配線・接続し、さらに絶縁保護膜を
被覆させるものにおいて、前記Ａｇ若しくはＡｇと他の
金属との化合物層と、絶縁保護膜との間に、酸化し易す
くかつ高融点の金属薄層を設けたことを特徴とする半導
体装置。(1) In a device in which Ag or a compound of Ag and another metal is attached to the surface of the element for wiring and connection, and further coated with an insulating protective film, the Ag or a compound layer of Ag and another metal; A semiconductor device characterized in that a thin metal layer that is easily oxidized and has a high melting point is provided between an insulating protective film. （２）前記特許請求の範囲第（１）項の記載において、
半導体装置は二つ以上のＰＮ接合を有し、そのＰＮ接合
の少くとも一つのＰＮ接合終端を、前記Ａｇ若しくはＡ
ｇと他の金属との化合物層にて短絡接続させるとともに
、前記酸化し易すくかつ高融点の金属薄層を、チタン族
、バナジウム族、Ｃｒ、Ｍｏ、Ｗのいずれか一つとする
ことを特徴とする半導体装置。(2) In the statement of claim (1),
The semiconductor device has two or more PN junctions, and at least one PN junction termination of the PN junctions is connected to the Ag or A
A short-circuit connection is made by a compound layer of g and another metal, and the thin metal layer that is easily oxidized and has a high melting point is made of one of titanium group, vanadium group, Cr, Mo, and W. semiconductor device.
JP59222446A 1984-10-22 1984-10-22 Semiconductor device Pending JPS61100952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59222446A JPS61100952A (en) 1984-10-22 1984-10-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59222446A JPS61100952A (en) 1984-10-22 1984-10-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61100952A true JPS61100952A (en) 1986-05-19

Family

ID=16782525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59222446A Pending JPS61100952A (en) 1984-10-22 1984-10-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61100952A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107687A (en) * 1997-03-18 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having interconnection and adhesion layers
US6417085B1 (en) 1999-07-02 2002-07-09 Micron Technology, Inc. Methods of forming a field effect transistor gate construction

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107687A (en) * 1997-03-18 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having interconnection and adhesion layers
US6417085B1 (en) 1999-07-02 2002-07-09 Micron Technology, Inc. Methods of forming a field effect transistor gate construction

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