JPH04168726A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04168726A
JPH04168726A JP2297699A JP29769990A JPH04168726A JP H04168726 A JPH04168726 A JP H04168726A JP 2297699 A JP2297699 A JP 2297699A JP 29769990 A JP29769990 A JP 29769990A JP H04168726 A JPH04168726 A JP H04168726A
Authority
JP
Japan
Prior art keywords
chip
stress
film
passivation film
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2297699A
Other languages
Japanese (ja)
Inventor
Kazutoshi Miyamoto
和俊 宮本
Jiro Murakami
二郎 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2297699A priority Critical patent/JPH04168726A/en
Publication of JPH04168726A publication Critical patent/JPH04168726A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent concentration to the peripheral section of a chip and a gold wire of stress from a molding resin, and to improve bond strength to defy peeling by forming irregularities and a slit to the surface of a passivation film. CONSTITUTION:Irregularities (h) are formed to the surface of a passivation film (b) protecting a chip (a), and the chip (a) is placed on a die pad (c). Outer leads (d) bring the chip (a) and the outside into contact electrically, and gold wires (e) connect the chip (a) to the leads (d). Even when stress is generated by the expansion and contraction of a molding resin (a molding package) (f) protecting the chip (a), the film (b), the die pad (c), the leads (d), the gold wires (e) and bonding pads (g), stress is dispersed by the irregularities (h) formed to the film (b). Accordingly, the concentration of stress to the peripheral section of the chip (a) and the gold wires (e) can be prevented while the bond strength of the resin (f) with the film (b) is improved, and both the resin (f) and the film (b) are difficult to be peeled.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、モールド樹脂の膨張・収縮応力がチップ表
面の周辺部に集中するのを防止する半導体装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that prevents expansion and contraction stress of a mold resin from concentrating on the periphery of a chip surface.

〔従来の技術〕[Conventional technology]

第６図は、モールド樹脂をパッケージとする従来の半導
体装置の一例を示す断面図である。FIG. 6 is a sectional view showing an example of a conventional semiconductor device using a molded resin as a package.

図において、（ａ）はチップ、（ｂ）はそのチップ（ａ
ｌを保護するパッシベーション膜、（Ｃ）はチップ（ａ
）を載せるダイパッド、（ｄ）はチップ（ａ）と外部と
の電気的コンタクトをとるための外部リード、（ｅ）は
チップ（ａ）と外部リード（ｄ）とを接続する金線、げ
）は（ａ）〜（ｅ）を保護するモールド樹脂である。In the figure, (a) is the chip, (b) is the chip (a
(C) is a passivation film that protects the chip (a
), (d) is an external lead for electrical contact between the chip (a) and the outside, (e) is a gold wire connecting the chip (a) and the external lead (d). is a mold resin that protects (a) to (e).

次に作用について説明する。Next, the effect will be explained.

モールド樹脂げ）が熱等によって膨張・収縮をした際、
この樹脂（ｆ）からパッシベーション膜（ｂｌ、ダイパ
ッド（Ｃ）、金線（ｅ）に応力が加えられる。When the mold resin expands or contracts due to heat etc.
Stress is applied from this resin (f) to the passivation film (bl), die pad (C), and gold wire (e).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置は以上のように構成されているので、
パッシベーション膜（ｂ）はほぼ−様な膜厚になってお
り、このパッシベーション膜（ｂ）の周辺部と金線（ｅ
）にモールド樹脂げ）からの応力が集中し、パッシベー
ション膜（ｂ）と金線（ｅ）にダメージを与えたり、パ
ッシベーション膜（ｂ）とモールド樹脂げ）との界面が
剥離するといった問題点があった。Conventional semiconductor devices are configured as described above, so
The passivation film (b) has an approximately -like film thickness, and the peripheral part of this passivation film (b) and the gold wire (e
There are problems such as stress from the mold resin burrs concentrating on ), damaging the passivation film (b) and the gold wire (e), and peeling off the interface between the passivation film (b) and the mold resin burrs. there were.

この発明は上記のような問題点を解決するためになされ
たもので、モールド樹脂から応力が加わっても、その応
力を分散させ、パッシベーション膜の周辺部と金線に加
わる応力を緩和できるとともに、パッシベーション膜と
モールド樹脂との密着強度を良くできる半導体装置を得
ることを目的とする。This invention was made to solve the above-mentioned problems, and even if stress is applied from the molding resin, it can disperse the stress and alleviate the stress applied to the peripheral part of the passivation film and the gold wire. An object of the present invention is to obtain a semiconductor device that can improve the adhesion strength between a passivation film and a molding resin.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、パッシベーション膜の表
面に凹凸又はスリットをつけたものである。A semiconductor device according to the present invention has a passivation film having irregularities or slits on its surface.

〔作用〕[Effect]

この発明における半導体装置は、モールド樹脂が膨張・
収縮し、チップに応力が加わっても、パッシベーション
膜表面の凹凸又はスリットにより応力か分散され、チッ
プ周辺部、全線に応力か集中することを防止する。また
、パッシベーション膜とモールド樹脂の蒸着強度か強く
なり、剥離しにくくなる。In the semiconductor device of this invention, the mold resin expands and
Even if stress is applied to the chip due to shrinkage, the stress is dispersed by the unevenness or slits on the surface of the passivation film, preventing stress from concentrating around the chip and all lines. In addition, the vapor deposition strength of the passivation film and molding resin becomes stronger, making it difficult to peel off.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第１図は、この発明の一実施例による半導体装置のチッ
プの上面図であり、第２図はその断面図である。FIG. 1 is a top view of a chip of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view thereof.

図において、（ａ）はチップ、（ｂ）はチップ（ａ）を
保護するパッシベーション膜であり、その表面には凹凸
（ｂ）がつけられている。（Ｃ）はチップ（ａｌを載せ
るダイパッド、（ｄ）はチップ（ａ）と外部との電気的
コンタクトをとるための外部リード、（ｅ）はチップ（
ａ）と外部リード（ｄ）とを接続する金線、（ｇ）は金
線（ｅ）の一端をボンドするためのポンディングパッド
、（ｆ＋は（ａ）〜（ｅ）、　（ｇ）を保護するモール
ド樹脂（モールドパッケージ）である。In the figure, (a) is a chip, (b) is a passivation film that protects the chip (a), and the surface thereof has irregularities (b). (C) is a die pad on which the chip (al) is placed, (d) is an external lead for making electrical contact between chip (a) and the outside, and (e) is a die pad on which the chip (al) is placed.
Gold wire connecting a) and external lead (d), (g) is a bonding pad for bonding one end of gold wire (e), (f+ is (a) to (e), (g) This is the mold resin (mold package) that protects the product.

このように構成された半導体装置において、モールド樹
脂げ）の膨張・収縮により応力か発生しても、パッシベ
ーション膜（ｂ）につけた凹凸（ｈ）によって応力が分
散され、チップ（ａ）の周辺部、金線（ｅｌに応力か集
中するのを防止できるとともに、モールド樹脂げ）とパ
ッシベーション膜（ｂ）の密着強度か良くなり両者が剥
離しにくくなる。In a semiconductor device configured in this manner, even if stress is generated due to expansion and contraction of the mold resin, the stress is dispersed by the unevenness (h) formed on the passivation film (b), and the stress is distributed around the peripheral area of the chip (a). In addition, it is possible to prevent stress from being concentrated on the gold wire (el), and the adhesion strength between the gold wire (el) and the passivation film (b) is improved, making it difficult for them to separate.

なお、上記実施例ではパッシベーション膜（ｂ）の表面
の全面に凹凸用）をつけたものを示したか、これは全面
でなく、一部につけてもよい。そして凹凸の形状は円板
外の形状でもよく、その場合も同様の効果を奏する。In the above embodiments, the passivation film (b) is provided with an uneven layer on the entire surface, but it may be applied not only on the entire surface but also on a part of the surface. The shape of the unevenness may be outside the shape of a disk, and the same effect can be achieved in that case as well.

また、上記実施例では、パッシベーション膜（ｂ）の表
面に凹凸（ｈ）をつけたが、第３図、第４図、第５図の
ようにスリット（ｉ）のようなものをつけてもよく、パ
ッシベーション膜（ｂｌの表面に段差をつけられるもの
であれば上記実施例と同様の効果を奏する。Further, in the above embodiment, the surface of the passivation film (b) is made uneven (h), but it is also possible to add something like a slit (i) as shown in FIGS. 3, 4, and 5. If a step can be formed on the surface of the passivation film (BL), the same effect as in the above embodiment can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、パッシベーション膜の
表面に凹凸又はスリットをつけたので、モールド樹脂か
らの応力がチップの周辺部と金線に集中するのを防止で
き、またパッシベーション膜とモールド樹脂は密着強度
が良くなり、剥離しにくくなるという効果がある。As described above, according to the present invention, since the surface of the passivation film is provided with unevenness or slits, it is possible to prevent stress from the mold resin from concentrating on the periphery of the chip and the gold wire. has the effect of improving adhesion strength and making it difficult to peel off.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例による半導体装置を示すチ
ップの上面図、第２図はそのチップの断面図、第３図乃
至第５図はこの発明の他の実施例を示すチップの上面図
、第６図は従来の半導体装置を示す断面図である。 図において、（ａ）はチップ、（ｂ）はパッシベーショ
ン膜、（Ｃ）はダイパッド、（ｄ）は外部リード、（ｅ
）は金線、げ）はモールド樹脂、（ｇ）はポンディング
パッド、（ｈｌは凹凸、（ｉ）はスリットである。 なお図中、同一符号は同−又は相当部分を示す。FIG. 1 is a top view of a chip showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of the chip, and FIGS. 3 to 5 are top views of chips showing other embodiments of the invention. 6 are cross-sectional views showing a conventional semiconductor device. In the figure, (a) is a chip, (b) is a passivation film, (C) is a die pad, (d) is an external lead, (e
) is gold wire, ridge) is molding resin, (g) is a bonding pad, (hl is unevenness, and (i) is slit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] （１）モールド樹脂をパッケージとする半導体装置にお
いて、チップのパッシベーション膜の表面に、凹凸又は
スリットをつけたことを特徴とする半導体装置。(1) A semiconductor device whose package is molded resin, characterized in that the surface of the passivation film of the chip is provided with irregularities or slits.
JP2297699A 1990-10-31 1990-10-31 Semiconductor device Pending JPH04168726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2297699A JPH04168726A (en) 1990-10-31 1990-10-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2297699A JPH04168726A (en) 1990-10-31 1990-10-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04168726A true JPH04168726A (en) 1992-06-16

Family

ID=17850018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2297699A Pending JPH04168726A (en) 1990-10-31 1990-10-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04168726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014116333A (en) * 2012-12-06 2014-06-26 Mitsubishi Electric Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014116333A (en) * 2012-12-06 2014-06-26 Mitsubishi Electric Corp Semiconductor device

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