JPS6345858A - Field effect transistor - Google Patents

Abstract

PURPOSE:To contrive the reduction in a parasitic capacitance by a method wherein an electrode for lead-out is integrally formed on the surface of each region of source and drain regions and each electrode of source and drain electrodes, and at the same time, the overlap of an element forming region with each electrode of the source and drain electrodes is lessened. CONSTITUTION:An Si oxide film 4 is formed on the surface of an element forming region 2 and a gate electrode 5, a source electrode 6 and a drain electrode 7 are formed on this Si film 4. With an electrode 10A for source region lead-out provided on the side surface of the source electrode 6 and part of the surface of a source region 8, an electrode 10B for drain region lead-out is integrally formed on the side surface of the drain electrode 7 and part of the surface of a drain region 9. According to such a way, the lead-out to the electrodes can be executed without using a contact hole. Moreover, the overlap of the element forming region 2 with the source and drain electrodes 6 and 7 can be lessened. As a result, the parasitic capacitance between the element forming region 2 and a substrate 1 can be reduced because the areas of the source region 8 and the drain region 9 become smaller.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to field effect transistors.

[Conventional technology]

In conventional silicon gate field effect transistors, an insulated gate film is formed on the surface of a silicon substrate using silicon oxide or the like, a gate electrode is formed on this insulated gate film using polycrystalline silicon of one conductivity type, and then the gate Impurities of opposite conductivity type are introduced into the silicon substrate in self-alignment with the electrodes to form source and drain regions, and then the entire surface is covered with an insulating film such as silicon oxide by vapor phase growth. Then, a contact hole is formed in this insulating film on the drain region using a photoetching method to expose the surfaces of the source and drain regions, and then a metal film such as aluminum is deposited on the entire surface, and then a contact hole is formed using a photoetching method again. The structure was such that a metal wiring pattern was formed and the source and drain regions were electrically drawn out to the surface.

[Problem that the invention seeks to solve]

However, in the conventional field effect transistor described above, the contact holes for electrically leading out the source and drain regions to the surface are formed by aligning and processing the mask during photoetching with respect to the gate electrode so that they do not come into contact with the gate electrode. Approximately 2 points from the gate electrode to ensure accuracy.
The need for micrometer separation has been an obstacle to improving the degree of integration of semiconductor monolithic integrated circuits in which a large number of transistors of this type are integrated.

Additionally, in general, from the channel region of a field effect transistor to the contact hole leading out the source or drain region, there is internal resistance of the semiconductor layer forming the source and drain regions, so in conventional field effect transistors, the internal resistance becomes large. However, it had drawbacks that hindered high-speed operation.

Furthermore, in conventional field effect transistors, the area required for providing contact holes in the source and drain regions increases the parasitic capacitance between the source region and the silicon substrate and between the drain region and the silicon substrate.
Another problem was that it hindered high-speed operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a field effect transistor that eliminates the above-mentioned drawbacks, has a high degree of integration, and is capable of high-speed operation.

[Means for solving problems]

The field effect transistor of the present invention includes an insulating isolation film formed on a semiconductor substrate and separating an element formation region, and a source made of a conductive material formed on the element formation region and separated from each other via a thin oxide film. an electrode, a gate electrode and a drain electrode, a source region and a drain region formed in self-alignment in the element formation region between the source electrode and the gate electrode and between the gate electrode and the drain electrode, a side surface of the source electrode and the source A source region extraction electrode formed integrally with a part of the surface of the region, and a drain region extraction electrode formed integrally with a side surface of the drain electrode and a part of the surface of the drain region. Consists of.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line xx' of an embodiment of the present invention.

In FIG. 1 (a>, (b)), a P-type silicon substrate 1
An insulating isolation film 3 made of a silicon oxide film with a thickness of approximately 6000 nm is formed on top to isolate the element formation region 2.
A silicon oxide film 4 with a thickness of 400 mm is formed on the surface of the element formation region 2, and a gate electrode 5, a source electrode 6, and a drain electrode 7 are formed on this silicon oxide film 4 with a thickness of 500 mm.
It is formed of a polycrystalline silicon film containing zero N-type impurities. In the element formation regions between the source electrode 6 and the gate electrode 5 and between the gate electrode 5 and the drain electrode 7, N-type source regions 8 and drain regions 9 are formed in a self-aligned manner, respectively.

Furthermore, a source region extraction electrode 10A is provided on the side surface of the source electrode 6 and a portion of the surface of the source region 8, and a drain region extraction electrode 10B is provided on the side surface of the drain electrode 7 and a portion of the surface of the drain region 9. are each formed integrally.

In this embodiment configured in this manner, the source region 8 and the drain region 9 are drawn out to the surface by forming contact holes on the side surface of the source electrode 6 and the source region 8, respectively, without using photoetching to form contact holes. This is performed by a source region extraction electrode 10A formed integrally with a part of the surface, and a drain region extraction electrode 10B integrally formed with a side surface of the drain electrode 7 and a part of the surface of the drain region 8. Furthermore, since the overlap between the element formation region 2 and the source electrode 6 and drain electrode 7 can be reduced to the level of mask alignment accuracy, the area of one source region and drain region can be further reduced.

Therefore, the parasitic capacitance between the source and drain regions and the silicon substrate is reduced.

In particular, if the source region extraction electrode 10A and the drain electrode extraction electrode 10B are formed of a thin film with high conductivity such as platinum or silicide film, the internal resistance existing from the channel of the field effect transistor to the drain electrode or source electrode can also be lowered.

Next, the manufacturing method of this example will be explained using the drawings.

FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in Figure 2(a), P
An insulating isolation film 3 made of a silicon oxide film with a thickness of 6,000 wafers is formed on one main surface of a silicon substrate 1 in the form of a mold to isolate an element forming region 2. Next, after thermal oxidation is performed to cover the surface of the element forming region 2 with a silicon oxide film 4 having a thickness of 400 nm, an Ox type polycrystalline silicon film having a thickness of approximately 5000 nm is deposited over the entire surface by vapor phase growth. let Subsequently, the polycrystalline silicon film is patterned using a photoetching method to form the gate electrode 5.
The source electrode 6 and the drain electrode 7 are sandwiched between the source electrode 6 and the drain electrode 7.
form.

Next, as shown in FIG. 2(b), after removing the silicon oxide film 4 using the source electrode 6, gate electrode 5, drain electrode 7, and insulating separation film 3 as masks, arsenic ions are implanted to form an element. N type source region 8 and drain region 9 are formed in region 2 .

Next, as shown in FIG. 2(c), after covering the entire surface with a photoresist film 12 with a thickness of 1.5 μm, part of the source electrode 6 and drain electrode 7 are formed on this photoresist film by photolithography. An opening 13 is provided to expose the. At this time, the area of the opening 13 is made as small as possible. That is, as shown in the plan view of FIG.
The line segments IJ, DC and the line segments ID, JC indicating the boundaries of are made as short as possible.

Next, as shown in FIG. 2(d), aluminum is deposited on the surface of the silicon substrate 1 by vacuum evaporation at a certain angle θ or more, which will be described later, with respect to the normal N of the silicon substrate 1, and the photoresist film 12 is An aluminum film 10 of about 2,000 layers is deposited on top. At this time, depending on how the angle θ is selected, the photoresist film 12 on the source electrode 6 and the gate electrode 5 serve as a mask for aluminum adhesion, so that the side surface of the gate electrode 5 on the source region side and the surface of the source region 8 near the gate electrode 5 Since aluminum is not deposited on the gate electrode 5
and source region 8 are not electrically connected through aluminum film 10, and for the same reason, gate electrode 5 and drain region 9 are also not electrically connected through aluminum film 10.

On the other hand, near the source electrode 6 and source region 8, the angle θ
Because the gate electrode 5 and the photoresist film 12 on the drain region 7 do not act as a mask for aluminum adhesion due to the selection of An aluminum film 10 is deposited on the portion in a self-aligned manner. Similarly, the aluminum film 10 is also deposited on the side surface of the drain electrode 7 and a part of the surface of the drain region 9.

Finally, the photoresist film 12 and the aluminum W deposited on the photoresist film 12 by the lift-off method.
By removing A10, the source electrode 6 and the source region 8 and the drain electrode 7 and the drain region 9 are electrically connected to each other as shown in FIGS. 1(a) and 1(b). An N-channel field effect transistor having an electrode 10A and a drain region extraction electrode 10B is obtained.

Next, the angle θ mentioned above will be explained using FIG. 2(c) and FIG. 3.

As shown in FIG. 2(C), an opening 13 is provided in the photoresist film 12, and the intersections of the outer periphery of the opening 13 and the gate electrode 5, drain electrode 7, and source electrode 6 are shown in FIG. A, B, C as shown.

..., L. It is advantageous in semiconductor monolithic integrated circuits to make the geometry of field effect transistors as small as possible, and this is also the purpose of the present invention, so line segment AB=CD=EF=F G = G H in FIG.
Engineering I J=KL=LA, design minimum dimension a, line segment BC=D
Assume that E=HI=JK is the design minimum alignment accuracy.

Based on this assumption, the gate electrode 5 in this embodiment in FIG.
The masking properties of the photoresist film 12 and the gate electrode 5 when depositing aluminum against the normal line of the silicon substrate 1 by vacuum evaporation are shown in FIG. It is only necessary to consider the surface portions of drain region 9 and source region 8 represented by line segments AF and KH.

A normal N to the silicon substrate 1 passing through a point P on the line segment AF,
A straight line N passing through point P and a point Q on the ridgeline of the resist film 12
′ is the angle formed by the normal N and the straight line N′
If aluminum is vacuum-deposited from an oblique direction at an angle larger than the angle α within the plane formed by the above, no aluminum will fly to the point P. In other words, the angle α means the limit angle for flying.

Similarly, when the angle formed by the normal M of the silicon substrate 1 passing through a point R on the line segment KH and the straight line M' passing between the point R and a point S on the ridgeline of the gate electrode 5 is β, When aluminum is vacuum-deposited obliquely at an angle smaller than angle β within the plane formed by line M and straight line M', angle β is at point R.
This means the limit angle at which aluminum will fly off.

The combination of points P and Q where the angle α is maximum is the point D
, or the case of points F and C, and the angle a at this time is
llIaX is the thickness of the silicon oxide film 4 and the gate electrode 5
If h is the sum of the film thickness of
becomes.

On the other hand, the combination of point R and point S where the angle β is the minimum is the case of the point R and the point S, or the case of the point H and the point G, and the angle β11. is βvain = jan −'(a/h). In practice, since aζ4b is 3a, (l I@II
X'= tan-'(0,4a/h), therefore (21
11ax<β1n. Therefore, the angle θ is α,,X
If the angle θ is chosen to be 〈θ〈β1゜, the angle θ will have the properties used in the examples.

Actually, in order to make aluminum fly onto the silicon substrate surface (here, the substrate is a circular plate with a diameter of 2r whose thickness can be ignored) at a constant angle θ or more with respect to the normal line of the silicon substrate 1, the center 0. Prepare a disk with radius R + 2r, and arrange the substrates so that the center of the silicon substrate is on the circumference of center O1 and radius R + r. On the normal line of the disk passing through the center O in the 0th order, θ = ja
The aluminum evaporation source may be placed at a point having a distance MH from the center 0 that satisfies n-'(R/H).

In the above embodiment, the source, gate, and drain electrodes are made of polycrystalline silicon, but MoR? W, silicides thereof, etc. may also be used.

〔Effect of the invention〕

As explained above, the present invention allows the extraction of the source region and the drain region to be carried out using the source region extraction electrode integrally formed on the side surface of the source electrode and a part of the surface of the source region, and the side surface of the drain electrode. This is done by using a drain electrode extraction electrode formed integrally with a part of the surface of the source region, and further reduces the overlap between the element formation region and the source and drain electrodes to the same level as the alignment accuracy of the mask. This has the effect of making it possible to further reduce the area of the source and drain regions.

Therefore, the parasitic capacitance between the source and drain regions and the semiconductor substrate and the internal resistance from the channel region to the source or drain electrode are reduced, resulting in a high degree of integration.
A field effect transistor capable of high-speed operation is obtained.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a plan view and a sectional view taken along the line xx' of an embodiment of the present invention, and FIGS. 2(a) to (d) illustrate a manufacturing method of an embodiment of the present invention. 3 is a cross-sectional view of the semiconductor chip shown in the order of steps for explanation, and FIG. 3 is a plan view showing an opening in the photoresist film in FIG. 2(c). 1... Silicon substrate, 2... Element formation region, 3...
- Insulating separation film, 4... silicon oxide film, 5... gate electrode, 6... source electrode, 7... drain electrode,
8... Source region, 9... Drain region, IOA・
...Source region extraction electrode, IOB...Drain region extraction electrode, IOC...Aluminum film, 12...
Photoresist film, 13...opening part. Cow 1 Figure 2 Mouth 3rd

Claims (1)

[Claims] an insulating separation film formed on a semiconductor substrate and separating an element formation region; and a source electrode, a gate electrode, and a drain electrode made of a conductive material formed on the element formation region and separated from each other through a thin oxide film. , a source region and a drain region formed in self-alignment in the element formation region between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and integrated with a side surface of the source electrode and a part of the surface of the source region. A field-effect transistor comprising: a source region lead-out electrode formed in the same manner; and a drain region lead-out electrode integrally formed on a side surface of the drain electrode and a part of the surface of the drain region. .