JPS634211B2 - - Google Patents

Info

Publication number
JPS634211B2
JPS634211B2 JP55072247A JP7224780A JPS634211B2 JP S634211 B2 JPS634211 B2 JP S634211B2 JP 55072247 A JP55072247 A JP 55072247A JP 7224780 A JP7224780 A JP 7224780A JP S634211 B2 JPS634211 B2 JP S634211B2
Authority
JP
Japan
Prior art keywords
shift register
scan
memory
circuit
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55072247A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56168270A (en
Inventor
Koji Hashiguchi
Takeo Koizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7224780A priority Critical patent/JPS56168270A/ja
Publication of JPS56168270A publication Critical patent/JPS56168270A/ja
Publication of JPS634211B2 publication Critical patent/JPS634211B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP7224780A 1980-05-30 1980-05-30 Logical device Granted JPS56168270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7224780A JPS56168270A (en) 1980-05-30 1980-05-30 Logical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7224780A JPS56168270A (en) 1980-05-30 1980-05-30 Logical device

Publications (2)

Publication Number Publication Date
JPS56168270A JPS56168270A (en) 1981-12-24
JPS634211B2 true JPS634211B2 (enrdf_load_stackoverflow) 1988-01-28

Family

ID=13483766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7224780A Granted JPS56168270A (en) 1980-05-30 1980-05-30 Logical device

Country Status (1)

Country Link
JP (1) JPS56168270A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142432A (ja) * 1983-12-28 1985-07-27 Fujitsu Ltd シリアル・データ・スキャン・イン/アウト方法
JP2641739B2 (ja) * 1988-07-29 1997-08-20 富士通株式会社 試験装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5939052B2 (ja) * 1977-03-15 1984-09-20 株式会社東芝 情報処理装置及び方法

Also Published As

Publication number Publication date
JPS56168270A (en) 1981-12-24

Similar Documents

Publication Publication Date Title
JP3890126B2 (ja) 集積回路のテスト用クロック発生方法および回路
JP2513904B2 (ja) テスト容易化回路
US6000051A (en) Method and apparatus for high-speed interconnect testing
JP4267716B2 (ja) Jtagによるsdram回路テスト方法
JPS62220879A (ja) 半導体装置
US5450418A (en) Pseudo master slave capture mechanism for scan elements
JPH0374796B2 (enrdf_load_stackoverflow)
US6341092B1 (en) Designing memory for testability to support scan capability in an asic design
JPS634211B2 (enrdf_load_stackoverflow)
JPS6123243A (ja) 論理集積回路
JP3094983B2 (ja) システムロジックのテスト回路およびテスト方法
KR20000069753A (ko) 코어 테스트 제어
US5130989A (en) Serial and parallel scan technique for improved testing of systolic arrays
US5426649A (en) Test interface for a digital circuit
EP1302776B1 (en) Automatic scan-based testing of complex integrated circuits
JPH06160489A (ja) バウンダリスキャン内部テスト方式
JPS6258025B2 (enrdf_load_stackoverflow)
JPS59211146A (ja) スキヤンイン方法
KR100503692B1 (ko) 고정논리값을출력하는수단의출력과회로의입력사이의접속테스팅장치
JPH112664A (ja) バウンダリスキャンレジスタ
EP0768538B2 (en) Method and tester for applying a pulse trigger to a unit to be triggered
JPH0391195A (ja) メモリ回路
JPS6161428B2 (enrdf_load_stackoverflow)
JPH0389178A (ja) 半導体集積回路
KR20040001334A (ko) 스캔 플립플롭을 구비한 반도체 집적 회로