JPS6341931A - Microprogram controller - Google Patents

Abstract

PURPOSE:To obtain a cheap and compact controlling device to cope with enlargement of a microprogram by providing a low speed but large capacity ROM, a small capacity and large bit width control memory, and a checking circuit that reads a microprogram copied in the control memory and makes parity check. CONSTITUTION:A low speed, large capacity ROM 3 is connected to a data bus 8 together at a high speed, small capacity control memory 2. The data bus 8 is a 16 bit bus, and the control memory 2 also inputs and outputs data in 16 bits. The data width of the ROM 3 is 8 bits, and connected to low-order of the data bus 8 by a data line 11. An instruction register 4 is connected to the data bus 8 and a microinstruction read out from the control memory 2 is set to it. A scan checking circuit 5 makes parity check of the microinstruction set to the instruction register 4, and when there is an error, reports to a controlling circuit 6 by an error line 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device, and more particularly to execution control of a microprogram in a microprogram control device.

[Conventional technology]

Conventionally, in a microprogram control device that is controlled by a built-in microprogram, the built-in microprogram is stored in a read-only storage device (hereinafter referred to as R).
This ROM is written in advance in the ROM.
A common method is to sequentially read and execute the contents of a microprogram when executing a microprogram.

Recently, the technology of such ROMs has made great progress, and ROMs with extremely large capacities are now manufactured and available at very low prices. However, such ROMs are generally slow in speed and have a data width of approximately 8 bits.

- High-performance MicroDurham controllers require high-speed operation of microprograms, so the microprogram can be read out at high speed, and the data width is wide at 24 bits and 32 bits for parallel operation. This is required. However, such requirements cannot be met with the current specifications of the ROMs mentioned above, and such microprogram control devices currently use small-capacity, high-speed ROMs.

Microprogram control devices are required to be capable of multi-Ia each year, and the capacity of micro 10 grams has also increased, making it extremely difficult to use such small-capacity ROMs in terms of both cost and volume. ing.

[Problem that the invention seeks to solve]

In the conventional high-performance microprogram control device with a built-in microprogram mentioned above, it is necessary to execute the microprogram at high speed, so a high-speed and expensive ROM is required.
g. It was important. In addition, it has become necessary to install and install microprograms on the θ-frame of the function, and the conventional method requires expensive ROM and a large amount of memory, making it costly in terms of cost. It is becoming. slow R
Although OM has a very large capacity and is manufactured at low cost, it has the drawback that such ROM specifications cannot be used in high-performance microprogram system 0'j devices.

[Means for solving problems]

The apparatus of the present invention includes a read-only storage means for storing a microprogram, and a read-only storage means for storing a microprogram. control storage means for storing the microprogram in the order in which it is executed; and a control storage means for reading out the microprogram stored in the control storage means in m×n bits (m is a natural number) each time prior to execution of the microprogram, and checking whether the microprogram is stored correctly.・scan check means for checking, and storage of the microprogram from the read-only storage means to the control storage means by an initialization signal input from the outside, checking the legitimacy of the stored microprogram, and checking the legitimacy of the microprogram. and a control means for controlling execution start.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the microprogram control device shown in FIG. 1, a low-speed, large-capacity ROM 3 is connected to a data bus 8 with a high-speed, small-capacity control memory. ! Connected with 2. The data bus 8 is a 16-bit bus, and the control memory 2 also inputs and outputs data using 16 bits. The data width of ROM 3 is 8 bits,
A data line 11 is connected to the lower part of the data bus 8, and a data line 12 is connected to the upper part of the data bus 8 via a buffer 7.
Connected by The address output from program counter 1 is connected to control memory 2 and ROM 3. An instance I/action register 4 is further connected to the data bus 8, and a microinstruction read from the control memory 2 is set therein. The scan check circuit 5 is connected to the instruction register 4 and checks the validity of the microinstruction set in the instruction register 4, and if an error occurs, it is notified to the control circuit 6 via an error line 16. The control circuit 6 is activated by an initialization signal from the initialization input 13, and controls data input/output, strobe transmission, etc. of each circuit.

FIG. 2 is an address map in the ROMB of this embodiment.

ROM3 has a data width of 8 bits and an address range of 0 to IFFF (16) in hexadecimal.
By 6), the upper 8 bits are 1000 (16) to I
The remaining lower 8 bits are stored in FFF (16).

Next, the operation of this embodiment will be explained.

When the microprogram control device shown in FIG. 1 is powered on, an initialization signal is input from the initialization input 13. This activates the control circuit 6 and sends a clear signal and a low-speed clock to the program counter 1 via the clock line 14. Program counter 1
outputs the microprogram address and controls memory 2 and R
Supply to OM 3. In addition, the control circuit 6 outputs an output enable signal to the ROM 3 and the buffer 7 to
Top 8 addressed microprograms in OMB
The bits are output to the data bus S via the buffer.

Next, the control circuit 6 outputs a write signal to the upper 8 bits of the control memory 2, and writes the upper 8 bits of the microprogram on the data bus 8 to the control memory 2. Since the access time of the ROM3 is long (because the ROM3 is a low-speed one), the write signal is output after the data on the data bus S is determined. Next, the control circuit 6 again outputs a clock to the program counter 1 to increment the count of the program counter 1. With this, ROM3 and control record +! :The next address of i2 is accessed, and the write operation of the microprogram at the next address of ROM 3 to control memory 2 is performed in the same manner as described above.

In this way, a similar operation is performed at the address after the limb in control memory 2 (
FFF (16)).

Since the microprogram is written in the ROM 3 as shown in Figure 2, the next time the program counter 1 counts up and reaches 1000 (16), the lower part of the microprogram is output to the data bus 8. Ru. At the same time, the control circuit 6 switches the write signal to the control memory 2 to the lower level side, and the lower level of the microprogram is written to the lower level of address O in the control memory. In the same manner as writing the upper part of the microprogram in this way, the control circuit 6 wakes up the program counter 1 one by one and performs the write operation up to the last address (IFFF (16)) in the control memory 2.

Next, the control circuit 6 disables the output of the ROM 3 and the output of the buffer 7, enables the output of the control memory 2, and transmits the high-speed clock to the program counter 1.
The send program counter 1 is reset to zero.

As a result, the control memory 2 outputs the previously written microprogram at address 0 to the data bus 8.

Next, the contents of this data bus 8 are set in the instruction register 4 and sent to the scan check circuit 5. The value of the microprogram sent to the scan check circuit 5 is subjected to a parity check, and if there is an error, the control circuit 6 is informed via the error line 16. When an error occurs, the clock output from the control circuit 6 to the program counter 1 is stopped and subsequent operations are prohibited.

If there is no error, the contents of successive addresses are checked one after another until the final address is checked.

If there is no error in all addresses as a result of checking up to the final address, the control circuit 6 returns the program counter 1 to zero, and the control circuit 2 sends the upper and lower parts of the microprogram 16 at a time via the data line 10. Read in bit width.

Thereafter, the microprogram is sequentially fetched in 16-bit width, and execution of the microprogram is started using a high-speed clock.

〔Effect of the invention〕

As explained above, the present invention includes a low-speed but large-capacity ROM, a small-capacity, wide-bit control memory, and a ROM.
By providing a control circuit that copies the microprogram from the control memory to the control memory, and a check circuit that reads the microprogram that has been copied to the control memory and performs a parity check, it is possible to create an inexpensive, compact, and high-performance device that can handle larger capacity microprograms. This has the advantage that it is possible to provide a microprogram control device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an address map diagram in the ROM. 1...Program counter, 2...Control memory, 3.
...ROM, 4...Instruction register, 5
...Scan check circuit, 6.. Control circuit, 7..
・Bassofa, 8 Data bus, 9・Address line, 1
1 data line, 11・data line, 12...data line 3
Initialize input, 14...Clock line 5, clock line, 16...Error line.

Claims (1)

[Claims] A read-only storage means storing a microprogram, and data read n bits at a time (n is a natural number) from the read-only storage means prior to execution of the microprogram are stored in the order in which the microprogram is executed. a control storage means for reading out the microprogram stored in the control storage means in units of m×n bits (m is a natural number) prior to execution of the microprogram, and checking whether the microprogram is stored correctly; a control means for controlling storage of the microprogram from the read-only storage means to the control storage means, checking the legitimacy of the stored microprogram, and starting execution of the microprogram by an initialization signal inputted from the outside; A microprogram control device comprising: