JPH09259039A - Method and device for controlling initialization for electronic computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently initialize a cache memory without burdening a processing means by setting a valid bit to all the lines of the cache memory and writing data set beforehand to the cache memory. SOLUTION: This initialization controller is constituted of a main memory 1, the cache memory 2 and a CPU 3 and is provided with a process for setting the value of an address tag to the respective lines of the cache memory 2, the process for setting the valid bit for indicating the validity of the data stored by the cache memory 2 to the respective lines beforehand, the process for writing the data set beforehand to the main memory 1 and the process for reading the value of the address tag, reading the data to which an address corresponding to the main memory 1 is set and writing the read data to the pertinent line of the cache memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an initialization control device for an electronic computer system, and more particularly to a cache memory initialization control.

[0002]

2. Description of the Related Art In a conventional computer system having a cache memory, there is a copy-back method as a method of transferring data from a main memory which is a main storage means to a cache memory. The copy-back method is a method of reading data (line fill) from the main memory in units of one line of the cache memory and writing the data in the cache memory. Further, in order to obtain information as to whether the data stored in the cache memory is valid or invalid, it is valid (va
The data of the line in which the lid) bit is set and the valid bit is set is considered to be valid.

At the time of initialization, the processor as the processing means and the main memory are simultaneously reset (POW ON
When reset), the cache memory invalidates the valid bits of all lines once. Even if the line fill is performed there and the data in the main memory is written, the data is invalid and a write miss occurs. Then, line filling is performed again, the valid bit is set, and then the data is written to the cache memory. Since the valid bit is set in the line in which the data is written, the data is treated as valid.

[0004]

In the conventional control of the cache memory as described above, the data read from the main memory and written to the cache memory after the POW ON reset is invalid because the valid bit is not set. It will be It must be written there after the valid bit is set. Moreover, the data written in the cache memory is indefinite data before the data set in the main memory is written and stabilized. As a result, the processing means is caused to perform unnecessary work, resulting in poor efficiency.

Therefore, there has been a demand for an initialization control method and apparatus for an electronic computer system which can efficiently initialize the cache memory without imposing a burden on the processing means.

[0006]

An initialization control method for an electronic computer system according to the present invention shows a step of setting an address tag value in each line of a cache memory and the validity of data stored in the cache memory. The step of setting the effective bit in each line in advance, the step of writing the preset data in the main storage means, the value of the address tag is read, and the data in which the corresponding address in the main storage means is set is read and read. Writing the issued data to the corresponding line of the cache memory. When initializing the cache memory,
The value of the address tag is set in each line of the cache memory. In addition, the effective bit is set in advance for all lines. After the preset data is written in the main storage means, the value of the address tag is read. The set data is read from the address of the main storage means corresponding to the address tag, and the set data is written in the line paired with the address tag. Since the valid bit is set in each line in advance, the data written in the cache memory is treated as valid data.

Further, the initialization control device for the electronic computer system according to the present invention sets the value of the address tag to each main line and the main storage means in which preset data is written at the time of initialization, and After writing the data set in the main memory means and the cache memory that sets the valid bit indicating the validity of each line in advance,
And a processing unit for reading the value of the address tag, reading the set data at the address of the main storage unit corresponding to the value of the address tag, and writing the data set in the line of the cache memory. When initializing the cache memory, the preset data is written in the main storage means, and the processing means reads out the data in which the address of the main storage means corresponding to the value of the address tag of the cache memory is set, The set data is written in the line of the cache memory which is paired with the tag value. Since the valid bit is set in each line in advance, the data written in the cache memory is treated as valid data.

[0008]

1 is a block diagram of an initialization control device for an electronic computer system according to an embodiment of the present invention. In the figure, 1 is a main memory, 2 is a cache memory, and 3 is a CPU. A circuit for clearing the valid bit is excluded from the cache memory 2 so that the valid bit is always set. The CPU 3 writes the write command (4
(Except the word write command), read the data from the main memory, and instruct the cache memory to write the data. In this embodiment, a 1-word write instruction is performed.

FIG. 2 is a block diagram of one line of the cache memory 2. TAG is a 21-bit address tag, V is a valid bit, D is a dirty bit, LWn (n = 1 to 1)
4) represents 32-bit longword data.

FIG. 3 is an operation flowchart of the initialization control device of the electronic computer system. In this embodiment, the address of the main memory 1 corresponding to the read address tag TAG is 1000. When POW ON is reset (S31), an initial value is set in the address tag TAG on the cache memory 2 (S32), and valid bits are set in all lines (S33). When preset data is written in the indeterminate main memory 1 and the data becomes stable (S34), the CPU 3 starts the processing of the 1-word write instruction (S35). The address tag TAG of the line to be written is read (S36), and the address of the main memory 1 corresponding to the address tag TAG (100
Data for 1 line from address 0 (addresses 1000 to 10)
Address 0F) is read (S37). The data is written word by word into any of the 32-bit long word data LW1 to LW4 of the cache memory 2 (S38). Since the valid bit V is set in all the lines in the cache memory 2, all the data in the cache memory 2 are treated as valid. Therefore, a write miss does not occur and the written data is treated as valid data. When the data is written, the dirty bit D is set to that line (S39). If another 1-word write command is not issued (S40), the process ends.

When the CPU 3 reads the data from the cache memory 2 after the writing to the cache memory 2 is completed, the CPU 3 is set to read only the data read from the main memory 1 and written in the cache memory 2. Therefore, even if the valid bit is set in all lines, undefined data is not read from other lines.

In the initialization control device for an electronic computer system as described above, the valid bits V of all the lines of the cache memory 2 are set in advance, so that a write miss occurs when a write command is issued during initialization. Since there is no need to refill the line,
No load on the processing means. In addition, the time required for the system as a whole can be reduced.

[0013]

As described above, according to the present invention, since the valid bit is set in all the lines of the cache memory and the preset data is written in the cache memory, a write miss does not occur in the cache memory. The written data is treated as valid. Therefore, the writing of data to the cache memory only needs to be done once, and the load on the processing means is not required.

[Brief description of drawings]

FIG. 1 is a block diagram of an initialization control device of an electronic computer system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of one line of a cache memory 2.

FIG. 3 is an operation flowchart of an initialization control device of an electronic computer system.

[Explanation of symbols]

 1 main memory 2 cache memory 3 CPU TAG address tag V valid bit D dirty bit LW1 to LW4 32 bit long word data

Claims (2)

[Claims] 1. A step of setting an address tag value in each line of the cache memory, a step of setting a valid bit indicating the validity of data stored in the cache memory in each line in advance, and data set in advance Writing in the main memory means, reading the value of the address tag, reading the set data at the corresponding address of the main memory means,
Writing the read data to a corresponding line of the cache memory, the initialization control method of the electronic computer system. 2. At the time of initialization, a main storage unit in which preset data is written and an address tag value is set in each line, and a valid bit indicating the validity of data is set in each line in advance. After writing the set data in the cache memory and the main storage unit, the value of the address tag is read, and the set data of the address of the main storage unit corresponding to the value of the address tag is read. And a processing means for writing the set data in a line of the cache memory.