JPS6339954U - - Google Patents
Info
- Publication number
- JPS6339954U JPS6339954U JP13235686U JP13235686U JPS6339954U JP S6339954 U JPS6339954 U JP S6339954U JP 13235686 U JP13235686 U JP 13235686U JP 13235686 U JP13235686 U JP 13235686U JP S6339954 U JPS6339954 U JP S6339954U
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating film
- amorphous silicon
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010408 film Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Description
第１図は本考案の実施例構成図、第２図はその
製造工程説明図である。
１……絶縁基板、２……絶縁膜、３……フオト
レジスト、４……コレクタ電極、５……コレクタ
層、６……ベース電極、７……ベース層、８……
エミツタ層、９……エミツタ電極、１０……薄膜
トランジスタ、１１……絶縁膜。
FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of its manufacturing process. DESCRIPTION OF SYMBOLS 1...Insulating substrate, 2...Insulating film, 3...Photoresist, 4...Collector electrode, 5...Collector layer, 6...Base electrode, 7...Base layer, 8...
Emitter layer, 9... Emitter electrode, 10... Thin film transistor, 11... Insulating film.
Claims (1)
タにおいて、ベース層と異なる第一層および該第
一層の電極を絶縁膜中に形成し、該第一層の上面
と絶縁膜の上面とをほぼ同一平面としその上部に
ベース層を配置するように構成したことを特徴と
する非晶質シリコン薄膜トランジスタ。 In an amorphous silicon bipolar thin film transistor, a first layer different from a base layer and an electrode of the first layer are formed in an insulating film, and the upper surface of the first layer and the upper surface of the insulating film are made substantially the same plane. An amorphous silicon thin film transistor characterized in that it is configured such that a base layer is disposed on top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13235686U JPS6339954U (en) | 1986-08-29 | 1986-08-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13235686U JPS6339954U (en) | 1986-08-29 | 1986-08-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6339954U true JPS6339954U (en) | 1988-03-15 |
Family
ID=31031665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13235686U Pending JPS6339954U (en) | 1986-08-29 | 1986-08-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6339954U (en) |
-
1986
- 1986-08-29 JP JP13235686U patent/JPS6339954U/ja active Pending