JPS6339226A - Loopbacik test system - Google Patents

Abstract

PURPOSE:To allow simple constitution to match phases at the time of loopbacking without using a variable delay memory by providing a random pattern detector on the reception side of a loop-back test turn-around terminal station and a random pattern generator on the transmission side. CONSTITUTION:A PN detector 10 in a B station 43 collates a signal PN transmitted from a tester 42 through an A station 41 with a time sequential pattern whose contents are predetermined. When they coincide with each other, a detection signal is outputted. At that time, a decoder 3 specifies a channel to be detected with the aid of a channel pulse CHP, and simultaneously specifies the channel number to be loopbacked to a loop pulse generator 4. According to a timing in a direction S from an PG 8, the loop pulse generator 4 generates a loop pulse to a corresponding channel phase in the direction S. At that time, an AND gate 12 switches a selector 6 to the side of a PN generator 11, to which a loop pulse is supplied. The PN pattern that the PN generator 11 generates is transmitted to a line SOUT through the selector 6, and inputted to the tester 42 through the A station 41.

Description

[Detailed description of the invention] [Summary] A random pattern detector is provided on the receiving side of a loopback test return terminal station, and a random pattern generator is provided on the transmitting side, and phase alignment during loopback can be performed using a simple configuration. Realize.

[Industrial application field]

The present invention relates to a loopback test method in high-speed multiplex communication, and more specifically, the present invention relates to a loopback test method in high-speed multiplex communication, and more specifically, a loopback test method is performed for each channel that is looped back at an arbitrary loopback terminal station in a system in which multiple information channels are time-division multiplexed and transmitted bidirectionally. Concerning improvement of loopback test.

With the advancement of digital communication technology, time division multiplex communication is widely used. In order to realize this digital multiplex communication, a loopback test is an important function that must be provided.

In such a loopback test, one side of a bidirectional signal is looped back to the other at each transmission terminal station in order to isolate failures or check when a line is opened. This is done to check whether

For example, as shown in FIG. 5, a PN signal (
A random pattern) is inserted and looped back only to the channel designated by the 8th station 43 from the R direction (from the A station to the 8th station direction) to the S direction (from the B station to the A station direction). Then, by separating the channel at the A station 41 and inputting it to the tester 42, it is possible to check whether the transmitted PN signal is correctly looped back.

The frame structure of information transmitted between stations is, for example, as shown in FIG.
(It is assumed that the information channel is configured to include a fixed information channel (HO~Y(.) and a housekeeping (HK) channel.The information channel is a high-speed signal of several tens of bits to several hundred bits, is used for return instructions, communication of terminal status, etc.

Station A inserts into the HK channel a command indicating which channel of HO-Hn to call back to, and station B receives this and executes the call back according to the instruction.

As information and communication services become more sophisticated, functions such as those mentioned above will become available.
The need for this is increasing.

[Conventional technology]

Conventionally, as shown in FIG. 7, for example, a frame synchronization unit 1 synchronizes with a frame transmitted from an A station 41, and a pulse generator (PC) 2 is activated by this output. In addition, HK channel decoder (HK C
HDEC) 3 decodes the contents of the HK channel in synchronization with the pulse generator 2. When the content of this decoder 3 is a loopback command (for example, channel i), the decoder 3 generates a loopback pulse (pulse of phase in the S direction of channel i) from the loopback pulse generator 4, and selector (SE
L) Switch 6 from SIN to variable delay memory 5, and output the contents of memory 5 as 5OUT. For this purpose, the memory 5 takes in the channel information i transmitted from the A station 41 with the pulse from the pulse generator 2, and at the timing when the return pulse from the return pulse generator 4 is input, the memory 5 outputs the channel information i to the pulse generator (PG). 8 (frame synchronized by the frame synchronization unit 7), the channel information taken into the variable delay memory 5 is controlled to be output in the corresponding channel time period on the return side.

Generally, the frame phases in the R direction and the S direction are arbitrary, and in order to return a specific channel to the R-S direction, it is necessary to match the phases. 5 is used.

In this case, it is necessary to consider the amount of delay for one frame at most.

[Problem that the invention seeks to solve]

In this conventional device, the number of frame bits per frame is large (if the number of frame bits is large, a delay amount proportional to this number of bits is required, the capacity of the variable delay memory becomes large, and the hardware becomes extremely large.For example, the transmission speed is 140Mb/s
In the case of an 8KHz frame, one frame is 17,500 bits, making it a very large piece of hardware.

The present invention was created in view of these points, and an object of the present invention is to provide a loopback test method that can perform a loop hack test with a small amount of hardware.

[Means for solving problems]

FIG. 1 shows a principle block diagram of the loopback test method of the present invention.

In the figure, 10 is a random pattern (PN
) is a PN detector that detects the signal.

A PN generator 11 generates a predetermined time-series PN pattern in response to the folded pulse.

Reference numeral 9 denotes a folding control unit that switches inputs according to the PN detector 10 and folded pulses.

[For production]

The PN signal received at the return station is detected by a PN detector 10, and a detection signal is generated when it matches a predetermined time series pattern.

Further, when a loopback pulse is generated, the loopback control section 9 switches the input to the PN generator 11 side, and the PN pattern generated from the PN generator 11 is sent to the loopback test station.

In the present invention, a loopback test can be performed without using a delay memory by detecting a PN signal at a return station and inserting the PN signal into a return channel at a predetermined timing.

〔Example〕

FIG. 2 shows an embodiment of the present invention, in which the circuit shown in FIG. 3 is used as the PN generator 11, and the circuit shown in FIG. 4 is used as the PN detector 10. Note that the same reference numerals are used for the same parts as in FIG. 7, so redundant explanations will be omitted.

The PN generator 11 receives the clock CLK as shown in FIG.
AND gate 111 that takes the logical product of the output of the gate 111, a shift register 112 that is shifted by the output of the gate 111, Nante gates 113 and 114 that take the output of the register 112 as input, and a NOR gate 115 that takes the logic of the outputs of the gates 113 and 114. , an exclusive OR gate 116 that takes the exclusive OR of the output of the seventh stage and the output of the fifteenth stage of the shift register 112, and gate 116 and gate 1.
It is composed of a NOR gate 117 that takes the logic of the output of
Generate N patterns of signals.

The PN detector 10 receives the clock CLK as shown in FIG.
AND gate 101 that takes the logical product of and channel pulse
, a D-type flip-flop 102 that operates based on data and the output of the gate 101, an inverter 103 that inverts the output of the gate 101, and an exclusive-OR gate 104.
, a D-type flip-flop 105 operated by the output of the gate 104 and the output of the inverter 103, and the gate 10.
1 and the output of the flip-flop 105, the AND gate 106 has the same configuration as that in FIG.
It is composed of a generator 107.

The PN signal sent from the tester via station A is checked in the PN detector 10 against the pattern of the PN generator 107, and when a match is found, a "0" level signal is output. At this time, the channel to be detected by the decoder 3 is indicated by the channel pulse CHP, and
The channel number to be looped back is instructed to the loopback pulse generator 4. The folding pulse generator 4 receives this channel number and generates a folding pulse at the corresponding channel phase in the S direction based on the S direction timing from PO2.

When the PN detection 510 outputs a "0" level signal and the pulse generator 4 outputs a "1" level signal (return pulse), the AND gate 12 outputs a "1" level signal,
Switch the selector 6 to the I)N generator 11 side. At this time, the above-mentioned folded pulse is given to the PN generator 11. The generation timing of this folding pulse coincides with the phase of the folding channel to be tested in the S direction, and the PN
The PN pattern generated by the generator 11 has the same content as the PN pattern generated by the tester 42. Therefore, P sent to the 5OUT line via selector 6
When the N patterns are input to the tester 42 via the A station 41, it can be seen that the loop is functioning normally.

It should be noted that the same techniques can be implemented on wireless channels as well.

〔Effect of the invention〕

As described above, according to the present invention, a loop hack test can be performed with a simple configuration without using a variable delay memory. In particular, when dealing with high-speed signals, the conventional configuration using delay memory requires a very large capacity memory and is not suitable for LSI implementation, but the present invention requires less hardware. easily L
It has the advantage of being able to be integrated.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the loopback test method of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a detailed circuit diagram of the PN generator 11 according to the present invention, and FIG. is a detailed circuit diagram of the PN detector 10 according to the present invention, FIG. 5 is an explanatory diagram showing an outline of a multiplex communication system, FIG. 6 is an explanatory diagram of a frame structure in multiplex communication, and FIG. 7 is a conventional loopback test. FIG. 2 is an explanatory diagram of the method. 1 and 2, 1.7 is a frame synchronization unit, 2.8 is a pulse generator, 3 is a housekeeping channel decoder, 4 is a folding pulse generator, 6 is a selector, 10 is a PN detector, 11 is a PN generator, and 12 is an AND gate. +A theory of invention 70・tq 田Figure 1, Pi, ni&uu゛dFigure 2
+>Figure 3'9't'6A% =yx=,tJP,>mkz*
<i'y'''AI Figure 5 1 - Hi, low grade elementary school class 5 color day Figure 6

Claims (1)

[Scope of Claim] A method for performing a loopback test on a channel-by-channel basis between arbitrary transmission terminal stations of a multiplex communication system in which a plurality of information channels are time-division multiplexed and transmitted bidirectionally between transmission terminal stations, comprising: A decoder (3
), a pattern detector (10) that compares the random pattern received via the channel specified by the decoder (3) with a preset pattern, and a random pattern (PN) generator (11) that generates a random pattern that is the same as the random pattern that has been detected; A loopback control unit (9) for sending the output of the random generator (11) to the test side via a loopback channel to the test side for a designated channel is provided to perform a loopback test for each channel. Features a loopback test method.