KR930001379Y1 - Data transmission system - Google Patents

Abstract

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Description

Data transmission system

1 is a block diagram of a conventional data transmission system.

2 is a block diagram of a data transmission system according to the present invention.

3 is a block diagram of the synchronous clock signal generator of FIG.

4 is a detailed circuit diagram of FIG.

5a to 5g are voltage waveforms for explaining the operation of FIG.

* Explanation of symbols for main parts of the drawings

1 to 4: First and second terminal stations 2 to 3: First and second input / output devices

5 to 6 and: first and second synchronous clock signal generators

7 to 8: first and second delay parts 9: logic combination parts

10: signal inverting unit 11: clock signal generating unit

12 to 13: first and second dividers

The present invention relates to a data transmission system, and more particularly, to a data transmission system capable of receiving serial synchronous data without providing a synchronization clock signal or a common clock signal on a transmitting side.

In general, in order to transmit synchronous serial data, the synchronization clocks of the transmitter and the receiver must be exactly matched. Therefore, the transmitter transmits the synchronization clock together with the serial data to the receiver or provides the same clock in common to the transmitter and the receiver. I needed this. However, this necessitates a separate transmission line for the transmission of the synchronous clock, or an apparatus that allows the transmitting and receiving side to use the same clock is economically disadvantageous, accompanied by a disadvantage that the data transmission system for the transmission and reception is complicated.

Therefore, the purpose of the present invention is to provide a data transmission system that can solve the above-mentioned disadvantages by enabling data transmission and reception without providing a synchronization clock or a common synchronization clock at the transmitting side.

The data transmission system of the present invention is connected to four main paths from the first terminal station 1 to control the input and output of data, and the first four input and output devices 2, and the four transmissions of the first input and output device 2 A second input / output device (3) connected from a furnace to control input / output of data, and serial data from the first terminal station (1) connected from four transmission paths of the second input / output device (3); In a data transmission system consisting of a second terminal station 4 which receives a synchronous clock signal or transmits serial data and a synchronous clock signal to the first terminal station 1, from the first terminal station 1 to 2; The first I / O device 2 connected by two transmission paths, the first I / O device 2, and the second I / O device 3 connected by two transmission paths from the first I / O device 2; And a second terminal station 4 connected from the second input / output device 3 by two transmission paths, A second synchronous clock signal generator 6 connected between the one transmission path of the second input / output device and the second terminal station 4, the one transmission path of the first input / output device 2 and the first terminal station 1; And a first synchronous clock signal generation device 5 connected between the plurality of signals.

The synchronous clock signal generating apparatus according to the present invention is configured to delay the input signal by inputting the first delay unit 7 for delaying the transmission data signal by a certain period and the output signal of the first delay unit 7 as a constant period. A second combiner 8, a logic combiner 9 for logically combining the output signals of the first and second delay units 7 and 8, and a clock signal generator for generating a clock signal ( 11) and a first divider 12 which receives a signal from the clock signal generator 11 as input and divides the input signal by a predetermined period and receives a clear signal from the logic combination unit 9; A signal inversion unit 10 for inverting one output signal of the first divider 12 to provide a clock signal to the first delay unit 7 and the second delay unit 8, and the first divider The remaining output signal of (12) is input, and the input signal is divided by a certain period, and cleared according to the output signal of the logical combination unit 9. It is characterized by consisting of a second frequency divider (13).

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a conventional data transmission system. In the synchronous serial data transmission from the first terminal station 1 to the second terminal station 4, the first data signal of the first terminal station 1 and The first synchronous clock signal is transmitted to the second input / output device 3 via the first input / output device 2. The second input / output device 3 inputs the first data signal and the first synchronous clock signal transmitted from the first input / output device 2 to the second terminal station 4 to complete the data.

Conversely, the transmission of the second data signal and the second synchronous clock signal from the second terminal station 4 to the first terminal station 1 is the same as the above-described operation.

That is, the first data transmission system requires four transmission paths.

2 is a block diagram of a data transmission system according to the present invention, wherein the first data signal from the first terminal station 1 is transmitted to the second terminal station 4 via the first and second input / output devices 2 and 3. The first data signal via the second input / output device (3) is applied to the second clock signal generating device (6) to generate a synchronous clock signal in the device (6), By being supplied to the second terminal station 4, the synchronous serial data of the first terminal station is accurately synchronized to complete the transmission to the second terminal station 4. As shown in FIG.

Conversely, the synchronous second data signal from the second terminal station 4 is also transmitted by the second and first input / output devices 3 and 2 and the first synchronous clock signal generating device 5 in the same manner as above. Will complete.

That is, FIG. 2 can transmit and receive data as two transmission lines.

FIG. 3 is a block diagram of the synchronous clock signal generator of FIG. 2, and since only the first and second synchronous clock signal generators 5 and 6 of FIG.

One output terminal of the first delay unit 7 which receives the transmission data from the transmission data transmission path via the second input / output device 3 is connected to the second delay unit 8, and the second delay unit ( One output terminal of 8) is connected to the second terminal station 4, and is connected to supply a signal to the logical combination section 9.

In addition, the remaining respective output terminals of the first and second delay units 7 and 8 are connected to the logical combination unit 9, respectively.

On the other hand, the clock signal generator 11 for generating the clock signal is connected to the first divider 12, and one output terminal of the first divider 12 is connected to the first divider via the signal inverting unit 10. And second delay portions 7 and 8. The remaining output terminals of the first divider 12 are connected to the second terminal station 4 via a second divider 13, and the output terminals of the logic combiner 9 are provided to the first and second dividers. It is connected to the cycles 12 and 13.

Referring to the operation of the present invention configured as described above are as follows.

The clock signal 11 generated by the clock signal generator 11 is divided into two, for example, by the first divider 12. One output signal of the first divider 12 is inverted by the signal inversion unit 10 to provide a clock signal to the first and second delay units 7 and 8, and the other output signal is divided into a second divider ( 13) is supplied.

At this time, the transmission data signal via the second I / O device is delayed by one week in the first delay unit 7. At this time, one output signal whose transmission data signal via the second input / output device is delayed in the first delay unit 7 is supplied to the second delay unit 8, and the other output signal is supplied to the logical combination unit 9. The second delay unit 8 delays the input signal by one period, and supplies its one output signal to the logical combination unit 9 and transmits it to the second terminal station 4 at the same time. At this time, the remaining output signals of the second delay unit 8 are supplied to the logic combining unit 9, and the signals inputted from the logical combining unit 9 are combined to form the first divider 12 and the second. The frequency divider 13 is cleared. After the first and second frequency dividers 12 and 13 are cleared before the output signal of the second delay unit 8 is output, the second frequency divider 13 is removed. When the synchronous clock signal is generated, the output signal of the second delay unit 8 is input to the second terminal station 4 to complete reception.

4 is a detailed circuit of FIG. 3 and its configuration is as follows.

One output terminal of the divider ICU3, which is connected from the clock signal generator 5 and constitutes a hexadecimal counter or the like, is a signal delay composed of a D-flip flop circuit or the like via the inversion gate U8. One output terminal of the divider IC U1, which is connected to the clock terminals CLK1 CLK2 of the IC ICs U1 and u2 and the remaining output terminals are composed of a hexadecimal counter, is connected to the signal delay IC U2, and one input of the AND gate U5. The other terminal is connected to one input terminal of the AND gate U6. One output terminal of the signal delay IC U2 is connected to the second terminal station 4 and to the other input terminal of the AND gate U6. The remaining output terminal of the signal delay IC U2 is connected to the remaining input terminal of the AND gate U5. Each output terminal of the AND gates U5 and U6 is connected to the input terminal of the OR gate U7, and the output terminal of the OR gate U7 is connected to the clear terminals CLK1 and CLR2 of the frequency divider ICs U3 and U4. The output terminal of the divider IC U4 is configured to be connected to the second terminal station 4.

The operation of the synchronous clock signal generation device of the present invention configured as described above will be described with reference to FIGS. 5A to 5G.

The clock signal (figure 5 waveform) generated by the clock signal generator 11 is divided in two, for example, by the divider IC U3 (figure 5b).

One output (Fig. 5B) of the divider IC U3 is inverted at the inverting gate U8 to provide a clock signal to the signal delay ICs U1 and U2, and the remaining output is supplied to the divider IC U4.

At this time, the transmission data signal (FIG. 5C) via the second input / output device 3 is output by being delayed by one cycle in the signal delay IC U1 (FIG. 5D), and the one output signal thereof is the signal delay IC U2. The output of U7, which is delayed once more at (Fig. 5e) and generates the clear signal of divider ICs U3 and U4 as the outputs of the signal delay ICs U1 and U2, is always applied to the AND gates U5 and U6 in the time T1 to T2. Since the outputs are combined to become the "high" level (5f degrees), the divider ICs U3 and U4 are cleared. After the frequency divider ICs U3 and U4 are cleared, frequency division is started again from the time T2, and the synchronous clock signal divided by the frequency divider ICs U and U4 from the clock signal is " high " at " low " When the transition to the level, the second terminal station 4 recognizes the received data and completes the reception. The point T3 of FIG. 5g is referred to as a data sampling point. Here, the division ratio provided by the divider ICs U3 and U4 is determined so that the period of the synchronous clock signal is half of the input data period.

As described above, according to the present proposal, the data transmission path can be reduced by providing data transmission and reception without providing a synchronization clock or a common synchronization clock at the transmitting side, and thus, there is an advantage that it is economically advantageous.

Claims (6)

A first input / output device 2 connected from four transmission paths from the first terminal station 1 to control input / output of data, and connected from four transmission paths of the first input / output device 2 A second input / output device 2 for controlling input / output and four transmission paths of the second input / output device 3 to receive serial data and a synchronous clock signal from the first terminal station 1 or In a data transmission system composed of a second terminal station (4) for transmitting serial data and a synchronous clock signal to a first terminal station (1), which are connected by two transmission paths from the first terminal station (1). A first input / output device 2, a second input / output device 3 connected by two transmission paths from the first input / output device 2, and two transmission paths from the second input / output device 3; Between the second terminal station 4 to be connected, one transmission path of the second I / O device and the second terminal station 4 A second synchronous clock signal generation device 6 belonging to the first synchronous clock signal generation device 5 connected between the one transmission path of the first I / O device 2 and the first terminal station 1; Data transmission system, characterized in that. 2. The apparatus of claim 1, wherein the first and second synchronous clock signal generating apparatuses (5 and 6) each include a first delay unit (7) for delaying a predetermined period of transmission data signal, and the first delay unit (7). A second delay unit 8 for delaying a predetermined period of time by inputting an output signal of a signal; and a signal inversion unit for providing a clock signal to the first delay unit 7 and the second delay unit 8; 10) and the second divider 13 which is inputted with the remaining output signal of the first divider 12 to the predetermined period and divides the input signal to be cleared according to the output signal of the logic combination unit 9. And a data transmission system. 3. A data transmission system according to claim 2, wherein each of said first and second delays (7 and 8) consists of de-flip flops. 3. The data transmission system according to claim 2, wherein the signal inverting portion (10) is composed of an inverting gate. 3. A data transmission system according to claim 2, wherein each of said first and second dividers (12 and 13) consists of a counter. 3. The logic combination section (9) according to claim 2, wherein the logic combination section (9) has an AND gate (U5 and U6) as an input of the respective outputs of the first and second delay sections (7 and 8), and an output of the AND gates (U5 and U6). A data transmission system comprising an Oagate U7 having an input.