JPH01164138A - Diagnostic system for stuff multiplexing device - Google Patents

Abstract

PURPOSE:To diagnose the function of a device stably and moreover through simple and easy circuit constitution even if jitter exists by controlling a counting operation in a write/read address counter by a prescribed way prior to diagnosis. CONSTITUTION:The phase comparison circuit 18 of a destuff circuit in a diagnosis circuit is operated prior to the diagnosis, and the counting operation of the write/read address counters 16,17 is controlled. Namely, for instance, in a case that the reference phase of the write address counter 16 leads that of the read address counter 17 and the phase difference of them is smaller than a prescribed value (value larger than allowable jitter width), the counting operation of the read address counter 17 is stopped for one bit so as to make the phase difference larger by one bit. Thus, a write address and a read address come to have the phase difference larger than the prescribed difference whichever is made to be a standard, and since a sufficient phase allowance is secured prior to the diagnosis, the function of the device can be diagnosed stably and moreover through the simple and easy circuit constitution even if the jitter is contained in input data.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention provides a method for converting a stuff multiplexer into a stuff multiplexer by comparing a separated high-order group signal and a low-order group signal as input/output data bit by bit. The present invention relates to a method for diagnosing a stuff multiplex converter, which diagnoses the functions of a stuff multiplexer.

[Prior Art] Regarding this kind of diagnosis, for example, there has been a paper entitled "Study of IN-0UT C:HECK Circuit of Multiplex Converter" (1981 National Institute of Electronics and Communication Engineers General Conference; Paper No. 2036). As shown, the high-order group signal is separated by a diagnostic circuit and compared bit by bit with the low-order group signal.

[Problems to be Solved by the Invention] However, in the case of the above-mentioned conventional technology, there is a problem that the circuit scale of the diagnostic circuit is larger than the multiplexer/demultiplexer as the main body.

In addition, a buffer memory is used to synchronize the data branched and separated from the higher-order group and data branched from the lower-order group bit by bit, but the phase difference between the input and output clocks of the buffer memory has not been discussed.

Therefore, if the number of memory stages is small and the phase difference between the write clock and the read clock is small, bit slips will occur if destuff jitter or input clock jitter is applied, even though the main body functions normally. There is a risk that abnormal diagnostic results may be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for diagnosing a stuffed multiplex converter that can stably diagnose the function of the device with a simple and easy circuit configuration even when jitter due to destuffing or the like is present.

[Means for solving the problem] The above purpose is to ensure that the difference between the write address and the read address to the diagnostic buffer memory has an allowable jitter for a certain training time before diagnosing each channel. This is achieved by controlling the counting operations in the write and read address counters so that the address width is greater than or equal to the width.

[Operation] That is, the reference phase of the write address counter and that of the read address counter are compared, and if the former is ahead of the latter and the phase difference is smaller than a predetermined difference (set to a value larger than the allowable jitter width), By stopping the counting operation of the read address counter by 1 bit, the phase difference is increased by 1 bit. Conversely, if the former is behind the latter and the phase difference is smaller than the predetermined difference, the count operation in the write address counter is stopped by 1 bit, thereby increasing the phase difference by 1 bit. This is what I did. Depending on the repetition of such control, the phase difference between the write address and the read address will be greater than a predetermined difference with respect to either the reference, and it is necessary to stop the control and perform the bit comparison operation from such a state where there is a phase margin. When starting, even if jitter is applied, the write address and read address will not overlap, and bit slips will not occur in the buffer memory.

[Example code] The present invention will be explained below with reference to FIGS. 1 to 3.

First, the stuff multiplex conversion apparatus according to the present invention will be described. FIG. 1 shows a schematic block configuration thereof. According to this, each piece of low-order group output data is multiplexed by a multiplexing circuit 2 via a stuff synchronization circuit 1, and is transmitted as high-order group output data to the stuff multiplexing converter of the other party, while the high-order group input data from the other party is After being separated by 3, it is obtained as lower-order group output data from the destuffing circuit 4. A stuff synchronization circuit is provided for low-order group input data, and a destuff circuit is provided for low-order group output data. The phase controlled oscillator 5 is used to create a clock RCK whose phase is controlled based on the reference phases WA and RA from the write and read address counters in the destuff circuit 4.

In the destuff circuit 4, low-order group data is written into a buffer memory by the write clock WCK from the separation circuit 3, and the low-order group data is read out from the buffer memory as low-order group output data by the write clock RCK. This is what is meant to be done.

The above is the general configuration and operation of a stuff multiplex converter, but the diagnostic circuit according to the present invention is added to the configuration as shown in the drawing. That is, a low-order group data selector 6, a low-order group clock selector 7, a high-order group data selector 8, a separation circuit 9. A diagnostic circuit consisting of a channel selector 10, a destuff circuit 11, a bit comparison circuit 12, and a control circuit 13 is added. In this case, the configuration of the separation circuit 9 is the same as that of the separation circuit 3, but the configuration of the destuffing circuit 11 is slightly different from that of the destuffing circuit 4. As shown in FIG. 2, the destuffing circuit 11 includes a destuffing detection circuit 14, a buffer memory 15, a write address counter 16, a read address counter 17, an OR gate 19 for inhibiting counting operation, and a phase comparator 18. However, the destuff circuit 4
This differs from the destuff circuit 11 in that the phase comparator 18 is not provided. This is because, in the destuffing circuit 4, the phase-controlled read clock RCK is created by the phase-controlled oscillator 5, but in the destuffing circuit 11, the read clock obtained from the low-order group clock selector 7 is created by the phase-controlled oscillator 5. Since it is used as the clock RCK, the phase comparator 18 is required. Specifically, the phase comparator 18 is composed of, for example, a D-type flip-flop, a differentiation circuit, and an AND gate for gate control.

Now, how the diagnosis is performed will be explained as follows.

That is, first, the selectors 6 to 8 are controlled by the control circuit 13.
, 10 are set to predetermined values, thereby selecting the data and read clock corresponding to the channel to be diagnosed. For example, when checking the operation of the receiving side separation circuit 3 and destuffing circuit 4, selector 8
In this case, the high-order group input data to the separation circuit 3 is selected and sent to the separation circuit 9. Separation circuit 9
After the channels are separated, a selector 10 selects a channel to be diagnosed, and in the destuffing circuit 11, the channel is destuffed by a destuffing detection circuit 14 and then written to a buffer memory 15. .

On the other hand, the destuffing circuit 4 corresponding to the channel to be diagnosed
Since the output data of and the corresponding output clock of the phase controlled oscillator 5 are selected by the selectors 6 and 7, the previously written data is read from the buffer memory 15 using the output clock as the read clock. , the data from the selector 6 are compared and verified on a bit-by-bit basis in a bit comparator circuit 12.

The diagnosis for the receiving side is as described above, and the diagnosis for the transmitting side is also similar. The selectors 6 and 7 select the low-order group input data to the stuff circuit corresponding to the channel to be diagnosed and the corresponding clock, while the selectors 8 and 10 select the high-order group output data and the channel to be diagnosed, respectively. By selecting , the same diagnosis as in the previous case is made. The bit comparison result obtained during diagnosis is processed by the control circuit 13, and each time the diagnosis for one channel is completed, the control circuit 13 switches the settings for selectors 6 to 8 and 10 to determine the next channel. This is something that has been moved to diagnosis.

By the way, selectors 6 to 8,
Immediately after switching the settings for 10, the phases of the write clock WCK from the separation circuit 9 and the read clock RCK from the selector 7 are arbitrary, and the count values of the write address counter 16 and read address counter 17 (address ) difference is also arbitrary. If diagnosis is to be performed immediately in such a state, it is impossible to perform the diagnosis stably. Therefore, prior to diagnosis, the control circuit 13 generates a quantity control signal C0NT for a certain period of time (address).
By activating the phase comparison circuit 18 and controlling the count operations of the write address counter 16 and read address counter 17, diagnosis is performed after a predetermined address phase difference is secured.

Figure 3 shows an example of the main part input/output signal waveforms at that time. In this example, the reference phase WA of the write address is higher than the reference phase RA of the read address immediately after the selector 6 to 8°10 is switched. This shows a case where the delay is within 1 bit of phase difference. Therefore, in such a case, during training (control signal C0NT="1") WA(7) rise IJ
When the RA(7) "1" state is detected and differentiated, a phase comparison pulse b is obtained from the phase comparator 18, which inhibits the write address counter 16 from counting by one bit via the OR gate 19. Therefore, the write address is delayed by one power count, and the phase difference between WA and RA is also 1.
This means that the bit size becomes larger.

As described above, a predetermined phase difference is secured between the write address and the read address by the phase control over a certain period of time, so if the generation of the control signal CONT is stopped and the diagnostic operation is started, Even if jitter within a predetermined phase difference is applied, the rising edges of WA and RA do not cross, and diagnosis can be performed stably without causing bit slips.

If WA is ahead of RA by a phase difference of less than 1 bit, a phase comparison pulse a is obtained as in the previous case, and this inhibits the count operation of the read address counter 17 by 1 bit. , a predetermined phase difference is ensured.

Note that in the above example, the predetermined phase difference is 1 bit, but if the pulse widths of WA and RA are widened, the predetermined phase difference can be easily increased according to the pulse width. Trillion. Furthermore, since the control signal C0NT is fixed to it_Ou in the destuffing circuit 4, it can operate normally, so the destuffing circuits 4 and 11 can have the same configuration. Further, in FIG. 1, blocks for B (bipolar)/U (unipolar) conversion and U/B conversion of input/output data are omitted, but this is not an essential problem for the present invention.

[Effects of the Invention] As explained above, according to the present invention, sufficient phase margin is secured prior to diagnosis, so even if input data contains jitter, the configuration can be stably and There is an effect that the function of the staff multiplex converter can be diagnosed easily and easily.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a general block configuration of a stuffing multiplex conversion device according to the present invention, FIG. 2 is a diagram showing a specific configuration of an example of a destuffing circuit in a diagnostic circuit according to the present invention, and FIG. 1 is a diagram showing essential input/output signal waveforms in an example for explaining training operations performed prior to one diagnosis; FIG. 6 to 8, 10... Selector, 5... Phase controlled oscillator, 4.11... Destuff circuit, 3, 9... Separation circuit, 12... Bit comparison circuit, 13... Control circuit,
15... Buffer memory, 16... Write address counter, 17... Read address counter, 18.
...Address phase comparator. 'Representative Patent Attorney Tadashi Akimoto Figure 1 Figure 2 Figure 1 et al. Figure 3

Claims (1)

[Claims] 1. A transmitter that multiplexes multiple asynchronous low-order group data into high-order group data through a buffer memory and transmits it to the other party, and separates the high-order group data from the other party and uses the buffer memory, phase comparator, and phase control oscillator. A diagnostic method for a stuff multiplex conversion device comprising a receiving section that outputs a plurality of low-order group data, the synchronized low-order group data separated and extracted from selected high-order group data being written into a diagnostic buffer memory. , before comparing and collating the low-order group data read from the diagnostic buffer memory with the selected low-order group data bit by bit using the selected low-order group clock as a read clock,
For a certain period of time, the write address and read address for the diagnostic buffer memory have a phase difference of more than a predetermined value.
A diagnostic method for a stuff multiplex conversion device characterized by controlling counting operations in write and read address counters.