JPS6338350U - - Google Patents
Info
- Publication number
- JPS6338350U JPS6338350U JP1986132951U JP13295186U JPS6338350U JP S6338350 U JPS6338350 U JP S6338350U JP 1986132951 U JP1986132951 U JP 1986132951U JP 13295186 U JP13295186 U JP 13295186U JP S6338350 U JPS6338350 U JP S6338350U
- Authority
- JP
- Japan
- Prior art keywords
- driver
- insulating layer
- disposed
- led element
- conductive pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Description
第１図は本考案の一実施例によるＬＥＤアレイ
ヘツドを示す断面図、第２図は本考案の一実施例
におけるＬＥＤアレイヘツドの電極取出し部を示
す断面図、第３図は従来のＬＥＤアレイヘツドを
示す断面図、である。 １……ＬＥＤアレイチツプ、２……ドライバＩ
Ｃ、７……支持基体、８……導電性支持基板、４
……配線パターン、９……絶縁層、５……ボンデ
イングワイヤ、１０……導体パターン。
ヘツドを示す断面図、第２図は本考案の一実施例
におけるＬＥＤアレイヘツドの電極取出し部を示
す断面図、第３図は従来のＬＥＤアレイヘツドを
示す断面図、である。 １……ＬＥＤアレイチツプ、２……ドライバＩ
Ｃ、７……支持基体、８……導電性支持基板、４
……配線パターン、９……絶縁層、５……ボンデ
イングワイヤ、１０……導体パターン。
Claims (1)
- 導電性支持基板上に導体パターンと絶縁層を設
け、この導電パターン上にＬＥＤ素子を有するＬ
ＥＤアレイチツプを配設し、上記絶縁層上に上記
ＬＥＤ素子を駆動するドライバＩＣとこのドライ
バＩＣの入出力信号を伝達する配線パターンを配
設したＬＥＤアレイヘツド。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986132951U JPS6338350U (ja) | 1986-08-28 | 1986-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986132951U JPS6338350U (ja) | 1986-08-28 | 1986-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6338350U true JPS6338350U (ja) | 1988-03-11 |
Family
ID=31032817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986132951U Pending JPS6338350U (ja) | 1986-08-28 | 1986-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6338350U (ja) |
-
1986
- 1986-08-28 JP JP1986132951U patent/JPS6338350U/ja active Pending