JPS62189135U - - Google Patents
Info
- Publication number
- JPS62189135U JPS62189135U JP1986076937U JP7693786U JPS62189135U JP S62189135 U JPS62189135 U JP S62189135U JP 1986076937 U JP1986076937 U JP 1986076937U JP 7693786 U JP7693786 U JP 7693786U JP S62189135 U JPS62189135 U JP S62189135U
- Authority
- JP
- Japan
- Prior art keywords
- led
- wiring
- led chips
- common electrode
- drive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Description
第１図は本考案の一実施例の構成を示す平面図
、第２図は従来のＬＥＤアレイヘツドの構成を示
す平面図。 １０……個別電極、１１……ＬＥＤアレイチツ
プ、１２……ワイヤ、１３ａ，１３ｂ……配線導
体、１４……バイヤホール、１５……ＬＥＤアレ
イ駆動ドライバ、１６……基板、１７ａ，１７ｂ
……下層配線導体、１７ｃ……上層配線導体。
、第２図は従来のＬＥＤアレイヘツドの構成を示
す平面図。 １０……個別電極、１１……ＬＥＤアレイチツ
プ、１２……ワイヤ、１３ａ，１３ｂ……配線導
体、１４……バイヤホール、１５……ＬＥＤアレ
イ駆動ドライバ、１６……基板、１７ａ，１７ｂ
……下層配線導体、１７ｃ……上層配線導体。
Claims (1)
- 列状に配列された複数のＬＥＤ素子の個別電極
を当該ＬＥＤ素子列の両側に有し且つ共通電極を
有するＬＥＤチツプを複数整列させると共に、前
記ＬＥＤ素子の個別電極と接続される第１の駆動
ドライバ及び前記各ＬＥＤチツプの共通電極と接
続される第２の駆動ドライバを備えるＬＥＤアレ
イヘツドにおいて、前記各ＬＥＤチツプの各個別
電極から前記第１の駆動ドライバに至る配線の抵
抗値と前記各ＬＥＤチツプの共通電極から前記第
２の駆動ドライバに至る配線の抵抗値との和を略
一定となる如く配線を設けたことを特徴とするＬ
ＥＤアレイヘツド。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986076937U JPS62189135U (ja) | 1986-05-23 | 1986-05-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986076937U JPS62189135U (ja) | 1986-05-23 | 1986-05-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62189135U true JPS62189135U (ja) | 1987-12-02 |
Family
ID=30924473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986076937U Pending JPS62189135U (ja) | 1986-05-23 | 1986-05-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62189135U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63254068A (ja) * | 1987-04-13 | 1988-10-20 | Kyocera Corp | 光プリンタヘツド |
-
1986
- 1986-05-23 JP JP1986076937U patent/JPS62189135U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63254068A (ja) * | 1987-04-13 | 1988-10-20 | Kyocera Corp | 光プリンタヘツド |