JPS6337670A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a high speed FET with a certain threshold voltage with good reproducibility and high through-put by a method wherein 2nd compound semiconductor layer which has a smaller electron affinity than 1st compound semiconductor layer and a control electrode which forms a Schottky barrier with a channel layer formed on the surface of a substrate are provided. CONSTITUTION:A nondoped GaAs layer 2 and a nondoped Al0.3Ga0.7As layer 3 are successively formed on a semi-insulating GaAs substrate 1 and an N-type layer 4 which is to be a channel layer is formed by Si implantation. Then a gate electrode 5 made of W-Al is formed on the channel layer 4 and Si is implanted with the gate electrode 5 as a mask to form N<+>type regions 6 which are to be source and drain regions. Then Si in the N-type layer 4 and the N<+> type regions 6 is activated by annealing and, after SiO2 is removed, a source electrode 7 and a drain electrode 8 which provide ohmic contacts and are made of AuGe/Ni/Au are formed on the N<+>type regions 6. With this constitution, the time for epitaxial growth can be reduced significantly and, further, an FET with a certain threshold voltage can be obtained with good reproducibility.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a compound semiconductor field effect transistor (hereinafter referred to as FET) having a heterojunction.

(Prior Art) FETs with this type of heterojunction are described in the literature Solid State Devices and Materials (Extende
d Abstracts of the 16th (
1984International)Confer
ence on 5solid 5tateDevice
s and Materials)+Kobe, 198
4, p, p, 355-358. FE generally with AtGaAs/GaAs heterojunction
T is a non-doped GaAs layer with a thickness of 1 μm as a buffer layer formed by epitaxial growth on a semi-insulating GaAs substrate.
A high-resistance GaAs layer and an n-type AtGa layer doped with impurities and having a lower electron affinity than this GaAs layer are laminated to a thickness of 100% and then form a heterojunction.
As layer and the case provided on this AtGaAs layer.
It is equipped with a gate electrode and a source electrode and a drain electrode formed on both sides of the gate electrode, and a two-dimensional quantized signal generated at the AtGaAs/GaAs hetero interface by a voltage applied to the gate electrode. AtGaAs with electron depletion
It is modulated by the layer's capacitance and mother capacitance, and operates as a field effect transistor.

(Problems to be Solved by the Invention) However, in the conventional method described above, the non-doped GaAs layer serving as the buffer layer is epitaxially grown to a thickness of 1 μm, which has the disadvantage that it takes a long time to grow. Further, the threshold voltage of an FET depends on the film quality of the buffer layer, and in order to obtain an FET with a constant threshold voltage with good reproducibility, it is necessary to stabilize the film quality of the buffer layer. In particular, the reproducibility of the activation rate after ion implantation into the epitaxial growth layer was not satisfactory.

Therefore, the present invention shortens the epitaxial growth time,
The object of the present invention is to provide a high-speed FET with high threshold voltage reproducibility.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides an FET having a heterojunction, in which a first compound semiconductor substrate such as GaAs, and a first compound semiconductor substrate directly or directly on this substrate are provided. A second compound semiconductor layer having a smaller electron affinity than the first compound semiconductor and laminated with an extremely thin buffer layer of compound semiconductor interposed therebetween; The formed channel layer,
The structure includes a control electrode forming a Schottky barrier formed on the channel layer, and the manufacturing method includes an extremely thin buffer layer of the first compound semiconductor grown directly or epitaxially on the substrate of the first compound semiconductor. A second compound semiconductor layer having a smaller electron affinity than the first compound semiconductor is epitaxially grown through the substrate, and impurity atoms serving as donors are ion-implanted from the surface of the substrate to form a layer at a depth including the substrate or the buffer layer. A temperature at which an n-type channel layer is formed and crystal defects present at the interface between the epitaxial growth layer on the substrate and the substrate are recovered, preferably 700 to 900.
Alternatively, an n-type layer of the first compound semiconductor is epitaxially grown on a thin buffer layer of the first compound semiconductor grown directly or epitaxially on the substrate of the first compound semiconductor,
An n-type second compound semiconductor layer having a smaller electron affinity than the first compound semiconductor is epitaxially grown on the n-type layer of the first compound semiconductor, and then crystals existing at the interface between the epitaxially grown layer on the base and the base are formed. Annealing is performed at a temperature at which defects are recovered.

(Function) As described above, according to the present invention, in a heterojunction FET, a buffer layer is not provided, or even if a buffer layer is provided, it is made of an extremely thin layer of about 200x or less, so that the vitaxial growth time is reduced compared to the conventional method. This can be significantly reduced. Furthermore, by annealing the channel layer at a depth that includes the substrate at a temperature that recovers crystal defects existing at the interface between the substrate and the epitaxial growth layer, FE can be achieved without providing a buffer layer.
The device characteristics of T are not deteriorated, and an FET with a constant value voltage can be obtained with good reproducibility.

(Example) FIGS. 1(a) to 1(d) are process sectional views of an FET for explaining the present invention in detail, and will be explained below with reference to the drawings.

First, as shown in FIG. 1(a), a non-doped GaAs layer 2 (buffer layer) with a thickness of 30X is formed on a semi-insulating GaAs substrate 1 by molecular beam epitaxial growth (MBE).
and 150X thick non-do fAto, 5G ao
, 7A s layer 3 is continuously grown.

Next, as shown in FIG. 1(b), Si was implanted from the surface at an energy of 30 kV and a dose of 2.6×10 c.
By performing ion implantation under the conditions of m 2 , an n layer 4 that will become a channel layer with a depth of about 600× is formed.

Next, as shown in FIG. 1(c), a W-At gate electrode 5 is formed on the channel layer 4, and using this gate electrode 5 as a mask, Si is implanted at an energy of 100 kV.
.

By performing ion implantation at a dose of 1.5 x 10''cm 2 , an n-layer 6 that will become a source/drain region is formed.

Next, 5iO7 (not shown) is deposited on the entire surface and annealed at a temperature of 800°C for 20 minutes to form the n-layer 4 and n-layer.
After activating the Si in the layer 6 and removing the 5IO2, a source electrode 7 is formed by AuGe/Ni/Au forming an ohmic contact on the n layer, as shown in FIG. 1(d).
and form the drain electrode 8.

The channel layer 4 includes an interface between the epitaxially grown layers (2, 3) and the semi-insulating GaAs substrate 1;
It is formed within the As substrate 1. So channel layer 4
The activation rate of Si implanted by the ion implantation method to form the semiconductor substrate 1 is determined by the quality of the semi-insulating GaAs substrate 1.

FIGS. 2(a) and 2(b) show current-voltage characteristics (hereinafter referred to as IV characteristics) of an enhancement mode FET and a deterioration mode FET according to the present invention, respectively. Both FETs have a case length of 08 μm and a dirt width of 10 μm. The FET according to the present invention includes an interface between an epitaxially grown layer and a substrate within the channel layer.
Since it is annealed at a temperature of ℃, Figure 2(a),
As can be seen from the IV characteristics in (b), no adverse effects due to traps or the like at the interface are observed.

As explained above, the epitaxial growth layer is grown by the molecular beam epitaxial growth method, and the growth rate of GaAs is 1 μm/hour, and the growth rate of Ato, 3Gao, and As is 1.4 μm/hour. G due to conventional structure
The growth time when a 1 μm thick aAs filler layer is provided is 1 hour and 39 seconds, but according to the structure of the embodiment of the present invention, the growth time can be shortened to 49 seconds. In addition, semi-insulating GaAs, for which the activation rate of Si implanted by ion implantation has been clarified.
By using the substrate, the controllability and reproducibility of the FET0 threshold voltage to be manufactured can be improved.

In the embodiments of the present invention, a case has been described in which a GaAs-based compound semiconductor is used as the substrate and the epitaxial growth layer, but other compound semiconductors having different electron affinities and similar lattice constants may be used as the substrate and the epitaxial growth layer. You can also do that. In addition, in the example, a non-doped GaAs layer 2 is grown to a thickness of 30X as a buffer layer, but this buffer layer is not provided and a kLo layer is directly grown on the substrate 1.
, 3G a o , 7 A 8 layers 3 may be grown. In addition, in the embodiment, after forming the n layer 6 and before forming the source electrode 7 and the drain stack 8, the temperature was 800°C.
The annealing condition is sufficient as long as it can recover the crystal defects present at the interface between the substrate 1 and the epitaxial growth layer. By using a heat-resistant metal for the source electrode and the drain electrode, the step may be performed before forming the gate electrode 5 or after forming the source electrode 7 and the drain electrode 8. Further, in the embodiment, the n-layer 4 as a channel layer is formed by ion implantation, but it may also be formed using an epitaxial growth method doped with a donor.

(Effects of the Invention) As described in detail above, according to the present invention, the Peter junction FET has a structure in which no buffer layer is provided or even if a buffer layer is provided, it is composed of an extremely thin layer of about 200X or less, and
The channel layer at a depth that includes the substrate is annealed at a temperature that recovers crystal defects existing at the interface between the substrate and the epitaxially grown layer, so high-speed FETs with a constant value voltage can be manufactured with good reproducibility and high throughput. I can do that.

[Brief explanation of the drawing]

FIGS. 1(,) to (d) are cross-sectional views of the FET process for explaining the present invention in detail, and FIGS. 2(,) to (b) are
) are the enhancement modes F according to the present invention, respectively.
It is a figure which shows the IV characteristic of ET and desolation mode F'ET. 1... Semi-insulating GaAs substrate, 2... Non-doped G
aAs layer, 3... non-doped AZ O,s Ga
o, 7A 8 layer, 4...n layer, 5.r-to electrode, 6.-source electrode, 7...drain electrode. Patent Applicant: Oki Electric Industry Co., Ltd. FET's IyV Life Plan (Tomisara) Figure 1 (α)
)) (7')Lz-Soi:/%-)j FET
I-V characteristics of JFET 1 element Maro 2 Figure 1, Display of the case 1986 Patent Application No. 180092 2, Name of the invention Semiconductor device and its manufacturing method 3, Person making the amendment Relationship with the case Patent issue Request Appointment Office (
105) 1-7-12-4 Toranomon, Minato-ku, Tokyo.
Agent Address (〒105) 1-711 Toranomon, Minato-ku, Tokyo
No. 12 No. 5, Subject of amendment: ``Detailed Description of the Invention'' column, ``Brief Description of Drawings'' column and drawings in the Clarification Document 1. 6 Contents of the amendment As shown in the attached sheet N',
Kuzu, 'S6, Contents of amendment (1) In the 13th line of page 3 of the specification, "1 μm or more" is amended to "approximately 1 μm." (2) On the 14th line of the same page in the same book, the word “high resistance” was replaced with “n”.
Correct it as "type". 1 Tsukasa (3) Same book! ``N-type'' on the 16th line of page + is corrected to ``p-type group.'' (4) ``Threshold voltage reproducibility'' and ``threshold voltage It is corrected as "control reproducibility". (5) The statement r 30 kv J on page 7, line 9 of the same book is corrected to r 30 keV J. (6) On the 10th line of the same page in the same book, the phrase ``by injection 600XJ'' is replaced by ``by injection AtGaA
600X from the surface of the s-layer. (7) The statement "Channel layer 4 is...determined" in lines 4 to 9 of page 8 of the same book has been corrected as follows. [Channel layer 4 is a thin epitaxially grown layer (2, 3
) and the interface between the semi-insulating GaAs substrate 1 and a region (peak) with a high concentration of implanted ions is formed in the substrate 1. The activation rate of the implanted ions in the AtGaAs layer is about 173 lower than that of the GaAs substrate 1, and the concentration of the implanted ions is also low, so the AtGaAs layer is completely depleted and does not function as a conductive layer. Therefore, depending on the activation rate of Si ions implanted into the GaAs substrate, the threshold voltage of the FET (
Vth) is determined. ” (8) On page 11, line 8 of the same book, “6... source electrode,
7...Drain conductivity. ” is replaced with “6...layers,”
7... Source electrode, 8-... Drain electrode. ” he corrected. (9) Drawings [Figures 1 (e) and (d) J are corrected as shown in the attached sheet.

Claims (1)

[Scope of Claims] 1) A first compound semiconductor substrate, and a first compound semiconductor having a smaller electron affinity than the first compound semiconductor, which is laminated directly on the substrate or via an extremely thin buffer layer of the first compound semiconductor. comprising: two compound semiconductor layers; a channel layer of the first and second compound semiconductor layers formed on a surface layer of the base; and a control electrode forming a Schottky barrier formed on the channel layer. A semiconductor element characterized by: 2) epitaxially growing a second compound semiconductor layer having a smaller electron affinity than the first compound semiconductor directly or epitaxially grown on the first compound semiconductor substrate; forming an n-type channel layer with a depth that includes the base or the buffer layer by ion-implanting impurity atoms to serve as donors from the surface of the base, and then forming an epitaxial growth layer on the base and the base. 1. A method for manufacturing a semiconductor device, comprising: annealing at a temperature at which crystal defects existing at the interface of the semiconductor device are recovered. 3) epitaxially growing an n-type layer of the first compound semiconductor on an extremely thin buffer layer of the first compound semiconductor grown directly or epitaxially on the substrate of the first compound semiconductor; a step of epitaxially growing an n-type second compound semiconductor layer having a smaller electron affinity than the first compound semiconductor layer on the layer, and then a temperature at which crystal defects existing at the interface between the epitaxially grown layer on the base body and the base body are recovered; 1. A method for manufacturing a semiconductor device, comprising the step of annealing the semiconductor device.