JPS6336025B2 - - Google Patents

Info

Publication number
JPS6336025B2
JPS6336025B2 JP57050997A JP5099782A JPS6336025B2 JP S6336025 B2 JPS6336025 B2 JP S6336025B2 JP 57050997 A JP57050997 A JP 57050997A JP 5099782 A JP5099782 A JP 5099782A JP S6336025 B2 JPS6336025 B2 JP S6336025B2
Authority
JP
Japan
Prior art keywords
station
computer
input
frame
occupied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57050997A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58169276A (ja
Inventor
Masakazu Okada
Hitoshi Fushimi
Seiichi Yasumoto
Takeshi Oonuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57050997A priority Critical patent/JPS58169276A/ja
Publication of JPS58169276A publication Critical patent/JPS58169276A/ja
Publication of JPS6336025B2 publication Critical patent/JPS6336025B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337Direct connection machines, e.g. completely connected computers, point to point communication networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
JP57050997A 1982-03-31 1982-03-31 マルチ計算機システム Granted JPS58169276A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57050997A JPS58169276A (ja) 1982-03-31 1982-03-31 マルチ計算機システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57050997A JPS58169276A (ja) 1982-03-31 1982-03-31 マルチ計算機システム

Publications (2)

Publication Number Publication Date
JPS58169276A JPS58169276A (ja) 1983-10-05
JPS6336025B2 true JPS6336025B2 (enrdf_load_stackoverflow) 1988-07-18

Family

ID=12874420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57050997A Granted JPS58169276A (ja) 1982-03-31 1982-03-31 マルチ計算機システム

Country Status (1)

Country Link
JP (1) JPS58169276A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0821010B2 (ja) * 1988-04-25 1996-03-04 富士通株式会社 アダプタ制御方式

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5622122A (en) * 1979-07-31 1981-03-02 Nec Corp Data processing system

Also Published As

Publication number Publication date
JPS58169276A (ja) 1983-10-05

Similar Documents

Publication Publication Date Title
US4511958A (en) Common bus access system using plural configuration tables for failure tolerant token passing among processors
US6728908B1 (en) I2C bus protocol controller with fault tolerance
US4354267A (en) Data transmission system utilizing loop transmission lines between terminal units
EP0119039A2 (en) Token access controller protocol and architecture
JPS5947906B2 (ja) ル−プ伝送システム
WO1992015162A1 (en) Method and apparatus for controlling data communication operations within stations of a local area network
KR970029126A (ko) 멀티프로세서 시스템
JPH0732401B2 (ja) 伝送制御方式
US7143206B2 (en) Method for controlling data transfer unit having channel control unit, storage device control unit, and DMA processor
US6105160A (en) Packet error detecting device in a DMA transfer
EP0094177B1 (en) Apparatus for direct memory-to-memory intercomputer communication
US6987776B1 (en) Multiplex communication method, the device and the system thereof
JPS59106021A (ja) バス構成方式
US20030154288A1 (en) Server-client system and data transfer method used in the same system
JPS6336025B2 (enrdf_load_stackoverflow)
EP1072977B1 (en) A system for initializing a distributed computer system and a method thereof
JPS6327741B2 (enrdf_load_stackoverflow)
JP2731878B2 (ja) 通信装置
JP4655733B2 (ja) リング型二重化ネットワークにおける受信方法及び装置
JPH0736173B2 (ja) 情報処理システム内の副ステーションを初期設定する方法。
JP2549849B2 (ja) 多重化メモリ装置
JP5076348B2 (ja) 共有メモリのアクセス方式
JP2000165424A (ja) ループ式データ伝送装置
JP3351581B2 (ja) データ中継装置
JPH0520783B2 (enrdf_load_stackoverflow)