JPS6327741B2 - - Google Patents

Info

Publication number
JPS6327741B2
JPS6327741B2 JP56101203A JP10120381A JPS6327741B2 JP S6327741 B2 JPS6327741 B2 JP S6327741B2 JP 56101203 A JP56101203 A JP 56101203A JP 10120381 A JP10120381 A JP 10120381A JP S6327741 B2 JPS6327741 B2 JP S6327741B2
Authority
JP
Japan
Prior art keywords
bus
loop
input
serial bus
output device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56101203A
Other languages
English (en)
Japanese (ja)
Other versions
JPS584427A (ja
Inventor
Ryoichi Takamatsu
Hiroaki Nakanishi
Masakazu Okada
Takayuki Morioka
Hideyuki Hara
Hirokazu Kasashima
Toshihisa Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56101203A priority Critical patent/JPS584427A/ja
Publication of JPS584427A publication Critical patent/JPS584427A/ja
Publication of JPS6327741B2 publication Critical patent/JPS6327741B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
JP56101203A 1981-07-01 1981-07-01 複数のシリアルバスル−プを有するマルチコンピユ−タシステム Granted JPS584427A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56101203A JPS584427A (ja) 1981-07-01 1981-07-01 複数のシリアルバスル−プを有するマルチコンピユ−タシステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56101203A JPS584427A (ja) 1981-07-01 1981-07-01 複数のシリアルバスル−プを有するマルチコンピユ−タシステム

Publications (2)

Publication Number Publication Date
JPS584427A JPS584427A (ja) 1983-01-11
JPS6327741B2 true JPS6327741B2 (enrdf_load_stackoverflow) 1988-06-06

Family

ID=14294367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56101203A Granted JPS584427A (ja) 1981-07-01 1981-07-01 複数のシリアルバスル−プを有するマルチコンピユ−タシステム

Country Status (1)

Country Link
JP (1) JPS584427A (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156376A (ja) * 1984-12-27 1986-07-16 Toshiba Corp 画像処理装置
JPS62102348A (ja) * 1985-10-29 1987-05-12 Toshiba Corp 共有入出力システム
JPH0787457B2 (ja) * 1986-03-20 1995-09-20 トヨタ自動車株式会社 故障情報伝送方法
US10691632B1 (en) * 2019-03-14 2020-06-23 DeGirum Corporation Permutated ring network interconnected computing architecture

Also Published As

Publication number Publication date
JPS584427A (ja) 1983-01-11

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