JPS6335307A - Methd of cutting semiconductor wafer - Google Patents

Methd of cutting semiconductor wafer

Info

Publication number
JPS6335307A
JPS6335307A JP61181016A JP18101686A JPS6335307A JP S6335307 A JPS6335307 A JP S6335307A JP 61181016 A JP61181016 A JP 61181016A JP 18101686 A JP18101686 A JP 18101686A JP S6335307 A JPS6335307 A JP S6335307A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
chip
cutting
chips
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61181016A
Other languages
Japanese (ja)
Other versions
JPH0770503B2 (en
Inventor
岡本 富美夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP18101686A priority Critical patent/JPH0770503B2/en
Publication of JPS6335307A publication Critical patent/JPS6335307A/en
Publication of JPH0770503B2 publication Critical patent/JPH0770503B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Dicing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体ウェハーをチップ単位に分割するための
切削方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a cutting method for dividing a semiconductor wafer into chips.

従来の技術 第3図、第4図を用いて従来の技術を説明する。Conventional technology The conventional technology will be explained using FIGS. 3 and 4.

第3図において、半導体ウェハー1をチップ単位に分割
する切削方法としては、チップ2の間のスクライブレー
ン3に高速回転する刃で一定の深さの溝を形成づる方法
がある。切削後の切削溝の中心たとえばx−x’ にお
ける半導体ウェハーの断面は第4図のようになる。切り
残し部分(斜線)の厚さしは130〜200μmである
In FIG. 3, as a cutting method for dividing the semiconductor wafer 1 into chips, there is a method of forming grooves of a constant depth in the scribe lane 3 between the chips 2 with a blade rotating at high speed. After cutting, the cross section of the semiconductor wafer at the center of the cut groove, for example along the line xx', is as shown in FIG. The thickness of the uncut portion (hatched) is 130 to 200 μm.

発明が解決しようとする問題点 スクライブレーン3を切削された半導体ウェハー1は次
に切り残し部分が割られて個々のチップとなる。このと
き切り残し部分は切削溝の底から半導体ウェハー1の裏
面に向かって、切削溝の側面あるいは半導体ウェハーの
裏面に対して45度の角度で用量することが多い。この
舅聞面4がチップ側面より外側に現れた場合、チップ2
のn面たとえばA−A’断面は第5図(a)に承りよう
になり、チップ表面の幅はチップ表面の幅より半導体ウ
ェハーの切り残し厚さtの約2倍だけ大きくなる。した
がって半導体ウェハーの切り残し厚みが大きいほど、チ
ップ載置板5の幅は、チップ2の本来の幅(チップ表面
の幅)より多くのマージンが必要となり、チップ載置板
5が大聖化づる。
Problems to be Solved by the Invention The semiconductor wafer 1 from which the scribe lanes 3 have been cut is then broken into individual chips with the uncut portions. At this time, the uncut portion is often dispensed from the bottom of the cut groove toward the back surface of the semiconductor wafer 1 at an angle of 45 degrees with respect to the side surface of the cut groove or the back surface of the semiconductor wafer. If this leg surface 4 appears outside the side surface of the chip, the chip 2
The n-plane, for example, the AA' cross section is shown in FIG. 5(a), and the width of the chip surface is larger than the width of the chip surface by about twice the uncut thickness t of the semiconductor wafer. Therefore, as the uncut thickness of the semiconductor wafer increases, the width of the chip mounting plate 5 needs to have a larger margin than the original width of the chip 2 (width of the chip surface), and the chip mounting plate 5 becomes more sacred.

一方、半導体ウェハー分v1時の男開面4が第5図(b
)に示すごとくチップ2の側面より内側に現れた場合に
はチップ周縁部にJ3いてチップの厚みが少なくなり、
後の組立工程でチップの欠けやクラックが発生しやすく
なる。この欠陥は半導体つエバーの切り残し厚みが大き
いほど生じゃすくなる。
On the other hand, the male open surface 4 at the time of the semiconductor wafer minute v1 is shown in FIG.
), if it appears inside the side of the chip 2, it will be located at the periphery of the chip and the thickness of the chip will be reduced.
Chips are more likely to chip or crack during the subsequent assembly process. This defect becomes more likely to occur as the uncut thickness of the semiconductor layer increases.

このことから、半導体ウェハーの切り残し厚みは小さい
ほど好ましいが、あまり小さくすると切削後の半導体ウ
ェハーがわずかな力や衝撃で割れやすくなり、半導体ウ
ェハー切削工程からチップ単位に分oJする工程までの
搬送あるいは洗浄作業の際に半導体ウェハーが割れる事
故が発生する。
For this reason, the smaller the uncut thickness of the semiconductor wafer is, the better; however, if it is too small, the semiconductor wafer after cutting will be more likely to break due to slight force or impact, and the semiconductor wafer will be transported from the semiconductor wafer cutting process to the process of dividing into chips. Alternatively, an accident may occur in which a semiconductor wafer breaks during cleaning work.

本発明は半導体つエバーの切り残し厚みを小さく、かつ
切削後に半導体ウェハーが割れる事故を防止しうる半導
体ウェハーの切削方法を提供するものである。
The present invention provides a method for cutting a semiconductor wafer, which can reduce the uncut thickness of the semiconductor wafer and prevent the semiconductor wafer from breaking after cutting.

問題点を解決するための手段 上記問題点を解決覆るため本発明は、半導体ウェハーの
チップ間の切削溝を半導体ウェハーの周縁部で浅く内部
で深く形成覆るものである。
Means for Solving the Problems In order to overcome the above-mentioned problems, the present invention covers cutting grooves between chips of a semiconductor wafer by forming shallow grooves at the peripheral edge of the semiconductor wafer and deep grooves inside the semiconductor wafer.

作用 このような切削方法によれば、製品となるチップが青ら
れる半導体ウェハーは、半導体つエバー周縁部での切り
残し厚みが大きく、切削後の半導体ウェハーでも、搬送
や洗浄作業に耐えつる強度が保たれる。
Effect: According to this cutting method, the semiconductor wafer from which the chips that become the product are made has a large uncut thickness at the periphery of the semiconductor die, and even the semiconductor wafer after cutting does not have enough strength to withstand transportation and cleaning operations. It is maintained.

実施例 以下本発明の半導体ウェハーの切削方法の一実施例を図
面に基づいて説明覆る。
EXAMPLE Hereinafter, an example of the semiconductor wafer cutting method of the present invention will be explained based on the drawings.

第1図は本発明を実施した半導体ウェハーの切削溝中心
における断面図である。半導体ウェハー11の周縁部、
たとえば半導体つエバー11の外周から10〜20IN
#Iの徒囲では切削溝を浅く(たとえば切り残し厚みt
lとして200μm以上)、それより内部では切削溝を
深く(たとえば切り残し厚みt2として70〜120μ
卯)形成する。上記切削を実施するための装置としては
従来のダイシングソーを用いることができ、刃の高さの
制御プログラムを変更することによって容易に実施でき
る。このように切削された半導体ウェハーは、製品とな
るチップがtlられる領域では切り残し厚みが小さく、
チップ単位に分割された優も勇間面の発生によるチップ
裏面幅の増減を小さくできる。したがって、第2図(a
)に示すように、チップ12の男開面14がチップ側面
より外側に現れた場合でも、チップ裏面の幅はチップ表
面の幅に比べて従来はど増加しない。このためチップ4
11!置板15の幅はチップ本来の幅(表面の幅)に対
して多くのマージンを必要どしない。また第2図(b)
に承りようにチップ12の舅聞面14がチップ側面より
内部に現れた場合でも、チップの厚みが小さくなる領域
はごくわずかに限られ、後の組立工程でのチップの欠け
やクラックの発生がほとんど無くなる。
FIG. 1 is a sectional view at the center of a cut groove of a semiconductor wafer in which the present invention is implemented. The peripheral part of the semiconductor wafer 11,
For example, 10 to 20 IN from the outer periphery of the semiconductor tube 11.
#I shallow cutting groove (for example, uncut thickness t
200μm or more), and the cutting groove is deeper inside than that (for example, the uncut thickness t2 is 70 to 120μm).
rabbit) to form. A conventional dicing saw can be used as a device for carrying out the above-mentioned cutting, and the cutting can be easily carried out by changing the blade height control program. The semiconductor wafer cut in this way has a small uncut thickness in the area where the chip that will become the product will be tl.
It is possible to reduce the increase or decrease in the width of the back surface of the chip due to the occurrence of the surface area divided into individual chips. Therefore, Fig. 2 (a
), even when the male open surface 14 of the chip 12 appears outside the side surface of the chip, the width of the back surface of the chip does not conventionally increase as much as the width of the front surface of the chip. For this reason, chip 4
11! The width of the placement plate 15 does not require a large margin with respect to the original width of the chip (width of the surface). Also, Figure 2(b)
Even if the bulge surface 14 of the chip 12 appears inside from the side surface of the chip, the area where the thickness of the chip becomes smaller is limited to a very small area, and chipping or cracking of the chip may occur during the subsequent assembly process. Almost disappears.

一方、製品チップがほとんど1りられない半導体ウェハ
ーの周縁部では切り残し厚みが大きくなっているため、
半導体ウェハーの切削後も充分な強度が維持され、搬送
や洗浄作業で半導体ウェハーが割れる事故を防止できる
On the other hand, the uncut thickness is large at the peripheral edge of the semiconductor wafer where almost no product chips can be removed.
Sufficient strength is maintained even after semiconductor wafers are cut, and accidents such as semiconductor wafers being broken during transportation or cleaning operations can be prevented.

発明の効果 以上木光明によれば、半導体ウェハーのチップ間の切削
溝を半導体ウェハーの周縁部で浅く、内部では深く形成
するので、チップ表面の幅はチップ表面の幅に比べて従
来はど大きくならないため、デツプ載置板の小型化が可
能となる。また、切削溝の浅いチップ周縁部でのかけや
クラックが発生し難く、切削された半導体ウェハーの搬
送、洗浄時に半導体ウェハーが割れる事故を防止できる
Effects of the Invention According to Mitsuaki Ki, the cutting grooves between the chips of a semiconductor wafer are formed shallowly at the periphery of the semiconductor wafer and deep inside the semiconductor wafer, so the width of the chip surface is not as large as the width of the chip surface. Therefore, the depth mounting plate can be made smaller. In addition, chips and cracks are less likely to occur at the peripheral edge of the chip where the cutting grooves are shallow, and it is possible to prevent the semiconductor wafer from breaking during transportation and cleaning of the cut semiconductor wafer.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は木yt明を実施した半導体ウェハーの切削溝中
心における断面図、第2図(a)(b)はぞれぞれ本発
明を実施した半導体ウェハーをチップ単位に分スηした
後のチップの断面図で、第2図(a)はチップ111!
置板を台む断面図、第3図は半導体ウェハーのスクライ
プレーンの一例を示す平面図、第4図は従来技術で切削
された半導体つエバーの切削溝中心における断面図、第
5図(aHb)はそれぐれ従来技術で切削された半導体
ウェハーをチップ中位に分割した後のチップ断面図で、
第5図(a)はチップU置板を含む断面図である。 11・・・半導体ウェハー、12・・・チップ、14・
・・男開而代理人   森  木  八  弘 第3図 第S図
Fig. 1 is a cross-sectional view at the center of the cut groove of a semiconductor wafer subjected to wood cutting, and Figs. 2 (a) and (b) are cross-sectional views of the semiconductor wafer subjected to the present invention after being divided into chips. FIG. 2(a) is a cross-sectional view of the chip 111!
3 is a plan view showing an example of a scribe plane for a semiconductor wafer, FIG. 4 is a sectional view at the center of the cutting groove of a semiconductor wafer cut by the conventional technique, and FIG. aHb) is a cross-sectional view of a chip after cutting a semiconductor wafer using the conventional technique into mid-chip parts.
FIG. 5(a) is a sectional view including the chip U placement plate. 11... Semiconductor wafer, 12... Chip, 14.
・Otoko Kaiji Agent Yahiro Moriki Figure 3 Figure S

Claims (1)

【特許請求の範囲】[Claims] 1、半導体ウェハーのチップ間の切削溝を半導体ウェハ
ーの周縁部で浅く、内部では深く形成する半導体ウェハ
ーの切削方法。
1. A semiconductor wafer cutting method in which cutting grooves between chips of a semiconductor wafer are formed shallowly at the periphery of the semiconductor wafer and deep inside.
JP18101686A 1986-07-30 1986-07-30 Semiconductor wafer cutting method Expired - Lifetime JPH0770503B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18101686A JPH0770503B2 (en) 1986-07-30 1986-07-30 Semiconductor wafer cutting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18101686A JPH0770503B2 (en) 1986-07-30 1986-07-30 Semiconductor wafer cutting method

Publications (2)

Publication Number Publication Date
JPS6335307A true JPS6335307A (en) 1988-02-16
JPH0770503B2 JPH0770503B2 (en) 1995-07-31

Family

ID=16093277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18101686A Expired - Lifetime JPH0770503B2 (en) 1986-07-30 1986-07-30 Semiconductor wafer cutting method

Country Status (1)

Country Link
JP (1) JPH0770503B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253140A (en) * 2011-06-01 2012-12-20 Disco Abrasive Syst Ltd Method for processing wafer
JP2017050319A (en) * 2015-08-31 2017-03-09 株式会社東京精密 Dicing method and dicing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253140A (en) * 2011-06-01 2012-12-20 Disco Abrasive Syst Ltd Method for processing wafer
JP2017050319A (en) * 2015-08-31 2017-03-09 株式会社東京精密 Dicing method and dicing device

Also Published As

Publication number Publication date
JPH0770503B2 (en) 1995-07-31

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