JPH0770503B2 - Semiconductor wafer cutting method - Google Patents

Semiconductor wafer cutting method

Info

Publication number
JPH0770503B2
JPH0770503B2 JP18101686A JP18101686A JPH0770503B2 JP H0770503 B2 JPH0770503 B2 JP H0770503B2 JP 18101686 A JP18101686 A JP 18101686A JP 18101686 A JP18101686 A JP 18101686A JP H0770503 B2 JPH0770503 B2 JP H0770503B2
Authority
JP
Japan
Prior art keywords
semiconductor wafer
chip
cutting
chips
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP18101686A
Other languages
Japanese (ja)
Other versions
JPS6335307A (en
Inventor
富美夫 岡本
Original Assignee
松下電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電子工業株式会社 filed Critical 松下電子工業株式会社
Priority to JP18101686A priority Critical patent/JPH0770503B2/en
Publication of JPS6335307A publication Critical patent/JPS6335307A/en
Publication of JPH0770503B2 publication Critical patent/JPH0770503B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体ウェハーをチップ単位に分割するための
切削方法に関する。
TECHNICAL FIELD The present invention relates to a cutting method for dividing a semiconductor wafer into chips.

従来の技術 第3図、第4図を用いて従来の技術を説明する。Conventional Technique A conventional technique will be described with reference to FIGS. 3 and 4.

第3図において、半導体ウェハー1をチップ単位に分割
する切削方法としては、チップ2の間のスクライブレー
ン3に高速回転する刃で一定の深さの溝を形成する方法
がある。切削後の切削溝の中心たとえばX−X′におけ
る半導体ウェハーの断面は第4図のようになる。切り残
し部分(斜線)の厚さtは130〜200μmである。
In FIG. 3, as a cutting method for dividing the semiconductor wafer 1 into chips, there is a method of forming a groove having a constant depth in a scribe lane 3 between the chips 2 with a blade which rotates at a high speed. The cross section of the semiconductor wafer at the center of the cutting groove after cutting, for example, XX 'is as shown in FIG. The thickness t of the uncut portion (diagonal line) is 130 to 200 μm.

発明が解決しようとする問題点 スクライブレーン3を切削された半導体ウェハー1は次
に切り残し部分が割られて個々のチップとなる。第5図
に示すように、このとき切り残し部分は切削溝の底から
半導体ウェハー1の裏面に向かって、切削溝の側面ある
いは半導体ウェハーの裏面に対して45度の角度で劈開す
ることが多い。この劈開面4がチップ側面より外側に現
れた場合、チップ2の断面たとえばA−A′断面は第5
図(a)に示すようになり、チップ裏面の幅はチップ表
面の幅より半導体ウェハーの切り残し厚さtの約2倍だ
け大きくなる。したがって半導体ウェハーの切り残し厚
みが大きいほど、チップ載置板5の幅は、チップ2の本
来の幅(チツプ表面の幅)より多くのマージンが必要と
なり、チップ載置板5が大型化する。
Problems to be Solved by the Invention The semiconductor wafer 1 that has been cut in the scribe lane 3 is then cut into uncut portions to form individual chips. As shown in FIG. 5, the uncut portion is often cleaved from the bottom of the cutting groove toward the back surface of the semiconductor wafer 1 at an angle of 45 degrees with respect to the side surface of the cutting groove or the back surface of the semiconductor wafer. . When the cleavage plane 4 appears outside the side surface of the chip, the cross section of the chip 2, for example the AA 'cross section, is the fifth area.
As shown in FIG. 6A, the width of the back surface of the chip is larger than the width of the front surface of the chip by about twice the uncut thickness t of the semiconductor wafer. Therefore, as the uncut thickness of the semiconductor wafer is larger, the width of the chip mounting plate 5 needs a margin larger than the original width of the chip 2 (width of the chip surface), and the chip mounting plate 5 becomes large.

一方、半導体ウェハー分割時の劈開面4が第5図(b)
に示すごとくチップ2の側面より内側に現れた場合には
チップ周縁部においてチップの厚みが少なくなり、後の
組立工程でチップの欠けやクラックが発生しやすくな
る。この欠陥は半導体ウェハーの切り残し厚みが大きい
ほど生じやすくなる。
On the other hand, the cleavage plane 4 when dividing the semiconductor wafer is shown in FIG. 5 (b).
When it appears inside the side surface of the chip 2 as shown in (3), the thickness of the chip becomes small at the peripheral portion of the chip, and chipping or cracking of the chip is likely to occur in the subsequent assembly process. This defect becomes more likely to occur as the uncut thickness of the semiconductor wafer increases.

このことから、半導体ウェハーの切り残し厚みは小さい
ほど好ましいが、あまり小さくすると切削後の半導体ウ
ェハーがわずかな力や衝撃で割れやすくなり、半導体ウ
ェハー切削工程からチップ単位に分割する工程までの搬
送あるいは洗浄作業の際に半導体ウェハーが割れる事故
が発生する。
From this, it is preferable that the uncut thickness of the semiconductor wafer is smaller, but if it is too small, the semiconductor wafer after cutting will be easily cracked by a slight force or impact, and it will be conveyed from the semiconductor wafer cutting step to the step of dividing into chips Accidents that a semiconductor wafer breaks during cleaning work.

本発明は半導体ウェハーの切り残し厚みを小さく、かつ
切削後に半導体ウェハーが割れる事故を防止しうる半導
体ウェハーの切削方法を提供するものである。
The present invention provides a method for cutting a semiconductor wafer, which has a small uncut thickness of the semiconductor wafer and can prevent an accident that the semiconductor wafer is broken after cutting.

問題点を解決するための手段 上記問題点を解決するため本発明は、半導体ウェハーの
チップ間の切削溝を、前記半導体ウェハーの周縁部では
第1の深さで形成し、前記周縁部よりも内部の領域にお
いては前記第1の深さよりも大であり前記半導体ウェハ
ーの厚みよりも小さくなる第2の深さで形成するもので
ある。
Means for Solving the Problems In order to solve the above problems, the present invention forms a cutting groove between chips of a semiconductor wafer at a first depth at a peripheral portion of the semiconductor wafer, and has a depth greater than that of the peripheral portion. The inner region is formed with a second depth which is larger than the first depth and smaller than the thickness of the semiconductor wafer.

作用 このような切削方法によれば、製品となるチップが得ら
れる半導体ウェハーは、半導体ウェハー周縁部での切り
残し厚みが大きく、切削後の半導体ウェハーでも、搬送
や洗浄作業に耐えうる強度が保たれる。
Effect According to such a cutting method, the semiconductor wafer from which the product chips are obtained has a large uncut thickness at the peripheral edge of the semiconductor wafer, and even the semiconductor wafer after cutting has sufficient strength to withstand conveyance and cleaning operations. Be drunk

実施例 以下本発明の半導体ウェハーの切削方法の一実施例を図
面に基づいて説明する。
EXAMPLE An example of a semiconductor wafer cutting method according to the present invention will be described below with reference to the drawings.

第1図は本発明を実施した半導体ウェハーの切削溝中心
における断面図である。半導体ウェハー11の周縁部、た
とえば半導体ウェハー11の外周から10〜20mmの範囲では
切削溝を浅く(たとえば切り残し厚みt1として200μm
以上)、それより内部では切削溝を深く(たとえば切り
残し厚みt2として70〜120μm)形成する。上記切削を
実施するための装置としては従来のダイシングソーを用
いることができ、刃の高さの制御プログラムを変更する
ことによって用意に実施できる。このように切削された
半導体ウェハーは、製品となるチップが得られる領域で
は切り残し厚みが小さく、チップ単位に分割された後も
劈開面の発生によるチップ裏面幅の増減を小さくでき
る。したがって、第2図(a)に示すように、チップ12
の劈開面14がチップ側面より外側に現れた場合でも、チ
ップ裏面の幅はチップ表面の幅に比べて従来ほど増加し
ない。このためチップ載置板15の幅はチップ本来の幅
(表面の幅)に対して多くのマージンを必要としない。
また第2図(b)に示すようにチップ12の劈開面14がチ
ップ側面より内部に現れた場合でも、チップの厚みが小
さくなる領域はごくわずかに限られ、後の組立工程での
チップの欠けやクラックの発生がほとんど無くなる。
FIG. 1 is a sectional view at the center of a cutting groove of a semiconductor wafer according to the present invention. The cutting groove is shallow in the peripheral portion of the semiconductor wafer 11, for example, in the range of 10 to 20 mm from the outer periphery of the semiconductor wafer 11 (for example, the uncut thickness t 1 is 200 μm).
Above, the cutting groove is formed deeper than that (for example, the uncut thickness t 2 is 70 to 120 μm). A conventional dicing saw can be used as a device for performing the above cutting, and can be easily prepared by changing a control program of the height of the blade. The semiconductor wafer cut in this way has a small uncut thickness in the region where a chip to be a product is obtained, and even after being divided into chips, the increase or decrease in the width of the chip back surface due to the generation of the cleavage plane can be reduced. Therefore, as shown in FIG.
Even when the cleavage plane (14) appears outside the side surface of the chip, the width of the back surface of the chip does not increase as compared with the width of the front surface of the chip. For this reason, the width of the chip mounting plate 15 does not require a large margin with respect to the original width (width of the surface) of the chip.
Further, as shown in FIG. 2 (b), even when the cleavage surface 14 of the chip 12 appears inside the side surface of the chip, the area where the thickness of the chip becomes small is very small. Almost no chipping or cracking occurs.

一方、良品の製品チップがほとんど得られない半導体ウ
ェハーの周縁部では切り残し厚みが大きくなっているた
め、半導体ウェハーの切削後も充分な強度が維持され、
搬送や洗浄作業で半導体ウェハーが割れる事故を防止で
きる。
On the other hand, since the uncut thickness is large in the peripheral portion of the semiconductor wafer where almost no good product chips are obtained, sufficient strength is maintained even after cutting the semiconductor wafer,
It is possible to prevent accidents where semiconductor wafers are broken during transportation and cleaning work.

発明の効果 以上本発明によれば、半導体ウェハーのチップ間の切削
溝を半導体ウェハーの周縁部で浅く、内部では深く形成
するので、チップ裏面の幅はチップ表面の幅に比べて従
来ほど大きくならないため、チップ載置板の小型化が可
能となる。また、切削溝の浅いチップ周縁部でのかけや
クラックが発生し難く、切削された半導体ウェハーの搬
送、洗浄時に半導体ウェハーが割れる事故を防止でき
る。
As described above, according to the present invention, the cutting groove between the chips of the semiconductor wafer is formed shallow at the peripheral portion of the semiconductor wafer and deep inside, so that the width of the chip back surface is not larger than that of the conventional chip width. Therefore, the chip mounting plate can be downsized. Moreover, cracks and cracks are less likely to occur at the shallow peripheral edge of the chip, and it is possible to prevent the semiconductor wafer from being broken during transportation and cleaning of the cut semiconductor wafer.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明を実施した半導体ウェハーの切削溝中心
における断面図、第2図(a)(b)はそれぞれ本発明
を実施した半導体ウェハーをチップ単位に分割した後の
チップの断面図で、第2図(a)はチップ載置板を含む
断面図、第3図は半導体ウェハーのスクライブレーンの
一例を示す平面図、第4図は従来技術で切削された半導
体ウェハーの切削溝中心における断面図、第5図(a)
(b)はそれぞれ従来技術で切削された半導体ウェハー
をチップ単位に分割した後のチップ断面図で、第5図
(a)はチップ載置板を含む断面図である。 11……半導体ウェハー、12……チップ、14……劈開面
FIG. 1 is a cross-sectional view of a semiconductor wafer according to the present invention at the center of a cutting groove, and FIGS. 2A and 2B are cross-sectional views of chips after dividing the semiconductor wafer according to the present invention into chips. 2A is a cross-sectional view including a chip mounting plate, FIG. 3 is a plan view showing an example of a scribe lane of a semiconductor wafer, and FIG. 4 is a cutting groove center of a semiconductor wafer cut by a conventional technique. Sectional view, FIG. 5 (a)
FIG. 5B is a cross-sectional view of a chip after dividing a semiconductor wafer cut by the conventional technique into chips, and FIG. 5A is a cross-sectional view including a chip mounting plate. 11 …… Semiconductor wafer, 12 …… Chip, 14 …… Cleaved surface

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体ウェハーのチップ間の切削溝を、前
記半導体ウェハーの周縁部では第1の深さで形成し、前
記周縁部よりも内部の領域においては前記第1の深さよ
りも大であり前記半導体ウェハーの厚みよりも小さくな
る第2の深さで形成することを特徴とする半導体ウェハ
ーの切削方法。
1. A cutting groove between chips of a semiconductor wafer is formed to have a first depth at a peripheral portion of the semiconductor wafer, and the cutting groove is larger than the first depth in a region inside the peripheral portion. There is formed a semiconductor wafer having a second depth which is smaller than the thickness of the semiconductor wafer.
JP18101686A 1986-07-30 1986-07-30 Semiconductor wafer cutting method Expired - Lifetime JPH0770503B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18101686A JPH0770503B2 (en) 1986-07-30 1986-07-30 Semiconductor wafer cutting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18101686A JPH0770503B2 (en) 1986-07-30 1986-07-30 Semiconductor wafer cutting method

Publications (2)

Publication Number Publication Date
JPS6335307A JPS6335307A (en) 1988-02-16
JPH0770503B2 true JPH0770503B2 (en) 1995-07-31

Family

ID=16093277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18101686A Expired - Lifetime JPH0770503B2 (en) 1986-07-30 1986-07-30 Semiconductor wafer cutting method

Country Status (1)

Country Link
JP (1) JPH0770503B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5846765B2 (en) * 2011-06-01 2016-01-20 株式会社ディスコ Wafer processing method
JP6569857B2 (en) * 2015-08-31 2019-09-04 株式会社東京精密 Dicing method and dicing apparatus

Also Published As

Publication number Publication date
JPS6335307A (en) 1988-02-16

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