JP2005123263A - Working method of semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a working method of a semiconductor wafer wherein deterioration of yield is prevented even if micro crack etc. occurs at a wafer end when the back of the semiconductor wafer is ground and the thinning (e.g. at most 100 μm) is performed. <P>SOLUTION: The semiconductor wafer 10 which is equipped with a chip region C at the central principal part of a surface is prepared. An annular cut portion 11 which penetrates the semiconductor wafer 10 is formed at a part of a peripheral portion E outside of the chip region C, and runs along outer periphery of the semiconductor wafer 10. After that, the back B of the semiconductor wafer 10 is ground, and thickness of the semiconductor wafer 10 is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor wafer processing method, and more particularly to a semiconductor wafer processing method applicable to a technique for grinding and thinning the back surface of a semiconductor wafer provided with an electronic circuit in a chip region.

  A semiconductor wafer provided with an electronic circuit in a chip region is a plurality of semiconductor chips that are diced and separated after the back surface is ground, and the semiconductor chips are mounted on a wiring board. There is a demand for thinner semiconductor chips due to the demand for higher density mounting.

In Patent Document 1, in order to reduce the stress when grinding the back surface of the semiconductor wafer, a groove is formed in advance on the surface of the semiconductor wafer to be diced from the surface side, and then the semiconductor is exposed until the groove is exposed. It describes that a semiconductor chip separated into pieces having a thickness of 50 μm or less is obtained by grinding the back surface of the wafer.
Special table 2001-523046 gazette

  By the way, as shown in FIG. 1, when the back surface of the semiconductor wafer 100 is ground and thinned (for example, 100 μm or less), the end portion 100a of the semiconductor wafer 100 has a tapered shape. The end portion 100a of 100 has a sharp knife shape. For this reason, microcracks and chipping (small wafer chipping) may occur at the end portion 100a of the semiconductor wafer 100 after grinding.

  In addition, when the thinned semiconductor wafer 100 is handled in a later process, the cracks are likely to advance in the effective chip region starting from microcracks and chipping generated at the end 100a of the semiconductor wafer 100. For this reason, there is a problem in that the yield at the time of obtaining a plurality of semiconductor chips diced by dicing the semiconductor wafer 100 is lowered.

  In the above-mentioned Patent Document 1, when the back surface of a semiconductor wafer is ground and thinned, microcracks and chipping are generated at the edge of the wafer, which causes a problem that the yield of the semiconductor wafer is reduced. Absent.

  The present invention was created in view of the above problems, and even when a microcrack or the like is generated at the edge of the wafer when the back surface of the semiconductor wafer is ground and thinned (for example, 100 μm or less), the yield is improved. An object of the present invention is to provide a method for processing a semiconductor wafer in which a decrease is prevented.

  In order to solve the above-mentioned problems, the present invention relates to a method for processing a semiconductor wafer, the step of preparing a semiconductor wafer having a chip region at the center main part of the surface, and the outer periphery of the semiconductor wafer outside the chip region. Forming a ring-shaped cut portion penetrating the semiconductor wafer at a peripheral portion along the edge, and reducing the thickness of the semiconductor wafer by grinding the back side of the semiconductor wafer. It is characterized by that.

  In one preferable aspect of the present invention, in the step of forming the cut portion, the cut portion is formed so as to penetrate from the back side to the surface side of the semiconductor wafer with the surface side of the semiconductor wafer attached to the support. Then, the ring-shaped portion at the peripheral edge of the semiconductor wafer is separated from the semiconductor wafer as a cutting portion. Subsequently, the semiconductor wafer is thinned (for example, 100 to 10 μm) by grinding the back side of the semiconductor wafer with the front side of the semiconductor wafer attached to the support.

  At this time, the ring-shaped cut portion is also ground, and the outer end portion thereof is processed into a sharp knife shape as described above, so that microcracks and chipping occur. However, since the cut portion is separated from the semiconductor wafer, there is no possibility that a crack will progress in the chip region of the semiconductor wafer when the semiconductor wafer is handled in a subsequent process. In addition, a new end is formed on the ground semiconductor wafer, and the end is not in the shape of a sharp knife, but a vertical plane is maintained. Cracks and chipping do not occur.

  Further, in order to solve the above-mentioned problems, the present invention relates to a method for processing a semiconductor wafer, comprising a step of preparing a semiconductor wafer having a chip region at a central central portion of a surface, the outside of the chip region, and the semiconductor wafer. Forming a ring-shaped cut portion having a depth that does not penetrate the semiconductor wafer from the back side of the semiconductor wafer, and grinding the back side of the semiconductor wafer in the peripheral portion along the outer periphery of the semiconductor wafer, And a step of reducing the thickness of the semiconductor wafer, and after the semiconductor wafer is ground, a groove having a depth of the cut portion is left in the semiconductor wafer.

  In the present invention, in the step of forming the cut portion, the cut portion is formed deeper than the thickness of grinding the semiconductor wafer from the back side of the semiconductor wafer, and in the step of reducing the thickness of the semiconductor wafer, Leave a groove with a shallow depth of cut.

  As a result, after grinding the semiconductor wafer, a groove is provided between the chip area and the end of the semiconductor wafer, so that cracks in the chip area are caused by microcracks or chipping generated at the end of the semiconductor wafer. Is prevented from progressing.

  Further, in order to solve the above-described problems, the present invention relates to a method for processing a semiconductor wafer, comprising a step of preparing a semiconductor wafer having a chip region at a central main portion of a surface, the outside of the chip region, and the semiconductor Forming a ring-shaped cut portion having a depth not penetrating the semiconductor wafer from the surface side of the semiconductor wafer at a peripheral portion along the outer periphery of the wafer; and a back surface of the semiconductor wafer, the cut portion being A step of reducing the thickness of the semiconductor wafer by grinding until it is exposed.

  In the present invention, the notch is formed deeper than the thickness after grinding of the semiconductor wafer from the surface side of the semiconductor wafer, and the back surface of the semiconductor wafer is ground until the notch is exposed. Is separated from the semiconductor wafer as a ring-shaped cutting portion.

  Even in this case, after grinding the semiconductor wafer, the edge where microcracking or chipping has occurred is separated as a ring-shaped cut portion, so that the crack may progress in the chip region of the semiconductor wafer. Is prevented. Moreover, what is necessary is just to set so that the depth of a notch part may become a little deeper than the thickness (for example, 10-100 micrometers) of the semiconductor wafer after grinding, when forming a notch part from the surface side of a semiconductor wafer.

  Therefore, since the cutting amount of the semiconductor wafer can be reduced as compared with the case where the cut portion is formed from the back side of the semiconductor wafer, when the cut portion is formed by the blade of the dicer, the life of the blade is lengthened and the production efficiency can be improved. it can.

  As described above, in the present invention, when the back surface of the semiconductor wafer is ground and thinned, even if microcracks or chipping occurs at the edge of the semiconductor wafer, the crack is prevented from progressing in the chip region. Therefore, the yield of semiconductor wafers can be improved.

  Embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
2 to 5 are views showing a semiconductor wafer processing method according to the first embodiment of the present invention.

  In the semiconductor wafer processing method according to the first embodiment of the present invention, as shown in FIG. 2A, first, a semiconductor wafer 10 such as a silicon wafer having a thickness of 600 to 800 μm is prepared. In the semiconductor wafer 10, a plurality of effective chip regions C are divided and provided in the central main part. In the effective chip region C, elements such as transistors (not shown), multilayer wiring (not shown) connected thereto, and the like are formed. Further, the outer peripheral edge E of the effective chip region C is a non-effective chip region. Then, the semiconductor wafer 10 is diced and separated so that the semiconductor wafer 10 is separated for each effective chip region C in a subsequent process, and thus the semiconductor chips are obtained.

  Thereafter, as shown in FIG. 2B, a support body 12 is prepared, and the element forming surface A (front surface) from which the effective chip region C of the semiconductor wafer 10 is exposed is attached to the support body 12, so that the semiconductor Assume that the back surface B of the wafer 10 faces upward. As the support 12, a material having rigidity such as a BG (Back Grinding) tape is used.

  Next, as shown in FIG. 3, the semiconductor wafer 10 adhered to the support 12 is fixed on a chuck table (not shown) of a dicer. Subsequently, the dicer blade 20 is rotated while being lowered and brought into contact with a predetermined portion of the peripheral edge E on the back surface B side of the semiconductor wafer 10, and a chuck table (not shown) to which the semiconductor wafer 10 is fixed is rotated. . As a result, as shown in FIG. 4A, a ring-shaped cut portion 11 is formed at the peripheral edge portion E along the outer periphery of the semiconductor wafer 10. Since the ring-shaped cut portion 11 can be formed by a general dicer without introducing a special device, there is no possibility of increasing the manufacturing cost.

  At this time, as shown in the detailed diagram on the upper right of FIG. 4A, the notch 11 is ring-shaped at the position of the peripheral edge E away from the end 10a of the semiconductor wafer 10 with a dimension W1 (for example, 1 to 5 mm). Formed. Further, the cut portion 11 is formed at the position of the peripheral edge E away from each effective chip region C with a dimension W2 (for example, 1 to 5 mm) so as not to be formed in the effective chip region C. Further, the width W3 of the cut portion 11 is formed to be 50 to 400 μm, for example.

  Furthermore, in 1st Embodiment, as shown in FIG.4 (b), the notch part 11 is penetrated and formed from the back surface B of the semiconductor wafer 10 to the element formation surface A, and a part of support body 12 is used. It is formed by cutting. The depth D of the cut formed in the support 12 is, for example, 20 to 30 μm.

  In this way, by forming the ring-shaped cut portion 11 at the peripheral edge E of the semiconductor wafer 10, the outer end portion of the peripheral edge E of the semiconductor wafer 10 is separated from the semiconductor wafer 10 as the ring-shaped cut portion 14. The Then, a new end portion 10 b that is a part of the cut portion 11 is formed in the semiconductor wafer 10. The new end portion 10b of the semiconductor wafer 10 is formed as a vertical surface instead of a tapered shape.

  Next, after the semiconductor wafer 10 adhered to the support 12 is taken out of the dicer, the back surface B of the semiconductor wafer 10 is ground by a grinder (not shown) as shown in FIG. The thickness of 10 is reduced to 200 μm or less (preferably 100 to 10 μm).

  At this time, the ring-shaped cutting portion 14 is also ground, and the end portion 10a is processed into a sharp knife shape as described above, so that microcracks and chipping occur. However, since the cutting portion 14 is separated from the semiconductor wafer 10, there is no possibility that cracks will progress in the effective chip region C of the semiconductor wafer 10 when the semiconductor wafer 10 is handled in a later process. In addition, since the new end portion 10b of the semiconductor wafer 10 after grinding is in a state in which the vertical surface is maintained, microcracks and chipping do not occur at the new end portion 10b of the semiconductor wafer 10.

  Subsequently, as shown in FIG. 5B, the semiconductor wafer 10 is peeled off from the support 12 and taken out. At this time, the ring-shaped cutting part 14 separated from the semiconductor wafer 10 is left on the support 12. Thereafter, as shown in FIG. 5C, the semiconductor wafer 10 is diced with the element formation surface A of the semiconductor wafer 10 facing upward, thereby obtaining a plurality of individual semiconductor chips 10x.

  As described above, in the semiconductor wafer processing method of the present embodiment, after forming the ring-shaped cut portion 11 penetrating the semiconductor wafer 10 at the peripheral edge E of the semiconductor wafer 10 adhered to the support 12, The back surface B of the semiconductor wafer 10 is ground by a grinder.

  For this reason, even if a microcrack or chipping occurs at the end portion 10a of the ring-shaped cut portion 14 separated from the semiconductor wafer 10, the semiconductor wafer 10 and the cut portion 14 are separated, so that the semiconductor wafer 10 is cracked. No longer proceeds. In addition, since the new end portion 10b of the semiconductor wafer 10 after the cut portion 11 is formed is a vertical surface, the occurrence of microcracks and chipping is prevented even if it is ground.

  Therefore, there is no possibility of cracks progressing in the effective chip region C of the semiconductor wafer 10, and thus a decrease in yield when the semiconductor wafer 10 is diced to obtain the semiconductor chips 10x is prevented.

  In the above-described embodiment, the cut portion 11 that penetrates the semiconductor wafer 10 from the back surface B side of the semiconductor wafer 10 is formed in the peripheral edge E, but the cut that penetrates it from the element formation surface A side of the semiconductor wafer 10. The part 11 may be formed in the same manner, and then the element forming surface A of the semiconductor wafer 10 may be attached to the support 12 and then the back surface B of the semiconductor wafer 10 may be ground.

(Second Embodiment)
6 and 7 are views showing a semiconductor wafer processing method according to the second embodiment of the present invention.

  In the second embodiment, when the cut portion is formed from the back side in the peripheral portion of the semiconductor wafer, the cut portion does not penetrate the semiconductor wafer. Detailed descriptions of the same elements and steps as those of the first embodiment are omitted.

  In the semiconductor wafer processing method of the second embodiment, first, as shown in FIGS. 2A and 2B of the first embodiment, a semiconductor wafer 10 is prepared, and an element formation surface A of the semiconductor wafer 10 is prepared. The (surface) side is attached to the support 12. Thereafter, as shown in FIG. 6A, a cut portion 11 is formed from the back surface B side in the peripheral edge E of the semiconductor wafer 10 by the same method as in the first embodiment. In the second embodiment, as shown in FIG. 6B, the cut portion 11 is adjusted to a depth that does not penetrate the semiconductor wafer 10, and is formed on the element formation surface A side of the semiconductor wafer 10 below the cut portion 11. A portion of the semiconductor wafer 10 having a thickness T (for example, 20 to 100 μm) is left. Then, when the back surface B of the semiconductor wafer 10 is ground in a subsequent process, a part of the cut portion 11 is left. Accordingly, the depth D of the cut portion 11 is set deeper than the thickness for grinding the semiconductor wafer 10.

  For example, when the back surface B of the semiconductor wafer 10 having a thickness of 800 μm is ground to reduce the thickness to 100 μm (the thickness to be ground is 700 μm), the depth D of the cut portion 11 is set to about 750 μm, and below that is about 50 μm. A portion of the semiconductor wafer 10 having a thickness T is left.

  In addition, the dimension W1 between the notch part 11 and the edge part 10a of the semiconductor wafer 10, the dimension W2 between the notch part 11 and the effective chip area C, and the width W3 of the notch part 11 are set similarly to the first embodiment. Is done.

  Next, as shown in FIG. 7A, similarly to the first embodiment, the back surface B of the semiconductor wafer 10 is ground by a grinder (not shown), so that the thickness of the semiconductor wafer 10 is 200 μm or less (preferably 100 to 10 μm). At this time, as described above, the depth D of the cut portion 11 is set deeper than the thickness of the semiconductor wafer 10 to be ground, so that the depth of the cut portion 11 is shallow at the peripheral edge E of the semiconductor wafer 10. A ring-shaped groove 11a is left.

  At this time, the end 10a of the semiconductor wafer 10 has a sharp knife shape, and microcracks and chipping occur in the end 10a. However, a groove 11a is formed between the effective chip region C and the end 10a of the semiconductor wafer 10. Therefore, it is possible to prevent cracks from progressing in the effective chip region C of the semiconductor wafer 10 during handling in a later process.

  Further, in the second embodiment, even after the back surface B of the semiconductor wafer 10 is ground, the peripheral edge E remains connected to the semiconductor wafer 10, which is convenient when handling in a subsequent process.

  Next, the semiconductor wafer 10 is peeled off from the support 12 and taken out. Thereafter, as shown in FIG. 7B, the semiconductor wafer 10 is diced with the element formation surface A of the semiconductor wafer 10 facing upward, thereby obtaining a plurality of separated semiconductor chips 10x.

  The semiconductor wafer processing method of the second embodiment has the same effects as those of the first embodiment. In addition, when the cut portion 11 is formed in the peripheral edge E of the semiconductor wafer 10, the semiconductor wafer 10 is prevented from penetrating, so that the cutting amount of the semiconductor wafer 20 by the dicer can be reduced. For this reason, compared with the first embodiment, the amount of wear of the blade 20 of the dicer is reduced and the life thereof is extended, and the production efficiency can be improved.

(Third embodiment)
8 and 9 are views showing a semiconductor wafer processing method according to the third embodiment of the present invention.

  In the third embodiment, a cut portion that does not penetrate the semiconductor wafer is formed on the peripheral portion of the semiconductor wafer from the element forming surface side, and then the back surface of the semiconductor wafer is ground to reduce the thickness. Detailed descriptions of the same elements and steps as those of the first embodiment are omitted.

  In the semiconductor wafer processing method of the third embodiment, first, a semiconductor wafer 10 similar to that of FIG. 2A of the first embodiment is prepared. Thereafter, as shown in FIGS. 8A and 8B, a cut portion 11 is formed in the peripheral edge E of the semiconductor wafer 10 from the element formation surface A (front surface) side. The cut portion 11 is formed with a depth D (for example, 50 to 250 μm) from the element forming surface A without penetrating the semiconductor wafer 10. In addition, the dimension W1 between the notch part 11 and the edge part 10a of the semiconductor wafer 10, the dimension W2 between the notch part 11 and the effective chip area C, and the width W3 of the notch part 11 are set similarly to the first embodiment. Is done.

  In 3rd Embodiment, after forming the notch part 11 from the element formation surface A side instead of the back surface B side of the semiconductor wafer 10, the back surface B of the semiconductor wafer 10 is ground and thinned. At this time, a ring-shaped part of the peripheral edge E of the semiconductor wafer 10 is separated from the semiconductor wafer 10. Accordingly, the depth D of the cut portion 11 is set deeper than the thickness of the semiconductor wafer 10 after grinding. For example, when the back surface B of the semiconductor wafer 10 having a thickness of 800 μm is ground to reduce the thickness to 100 μm, the depth D of the cut portion 11 is set to about 150 μm.

  Next, as illustrated in FIG. 9A, the element formation surface A of the semiconductor wafer 10 is attached to the support 12. Subsequently, as shown in FIG. 9B, similarly to the first embodiment, the back surface B of the semiconductor wafer 10 is ground by a grinder (not shown), so that the thickness of the semiconductor wafer 10 is 200 μm or less (preferably Is reduced to 100 to 10 μm).

  At this time, as described above, the depth D of the cut portion 11 formed on the peripheral edge E of the semiconductor wafer 10 from the element forming surface A side is set deeper than the thickness of the semiconductor wafer 10 after grinding. Therefore, as in the first embodiment, a part of the peripheral edge E of the semiconductor wafer 10 is separated from the semiconductor wafer 10 as a ring-shaped cutting part 14. Then, a new end portion 10 b having a vertical surface that is a part of the cut portion 11 is formed on the semiconductor wafer 10.

  Accordingly, as in the first embodiment, the end portion 10a of the ring-shaped cutting portion 14 is processed into a sharp knife shape to generate microcracks and chipping, but the cutting portion 14 is separated from the semiconductor wafer 10. When the semiconductor wafer 10 is handled in a subsequent process, there is no possibility that cracks will advance in the effective chip region C of the semiconductor wafer 10. In addition, since the new end portion 10b of the semiconductor wafer 10 after grinding maintains a vertical plane, microcracks and chipping do not occur at the new end portion 10b of the semiconductor wafer 10.

  Thereafter, as shown in FIG. 9C, in the same manner as in the first embodiment, after the semiconductor wafer 10 is peeled off from the support 12, the semiconductor wafer 10 is placed with the element formation surface A on the upper side. By dicing 10, a plurality of separated semiconductor chips 10 x are obtained.

  The third embodiment has the same effect as the first embodiment. Furthermore, in the third embodiment, since the cut portion 11 is formed from the element mounting surface A side of the semiconductor wafer 10, the depth D of the cut portion 11 is the thickness of the semiconductor wafer 10 after grinding (for example, 10 to 10). It may be set somewhat deeper than 100 μm). Therefore, in the third embodiment, since the depth D of the cut portion 11 can be remarkably shallower than in the first and second embodiments, the amount of wear of the blade 20 of the dicer is further reduced and its life is prolonged. Thus, production efficiency can be improved.

FIG. 1 is a cross-sectional view showing inconvenient points when a semiconductor wafer according to the prior art is ground and thinned. FIGS. 2A to 2B are views (No. 1) showing the semiconductor wafer processing method according to the first embodiment of the present invention. FIG. 3 is a diagram (part 2) illustrating the semiconductor wafer processing method according to the first embodiment of the present invention. FIGS. 4A to 4B are views (No. 3) illustrating the semiconductor wafer processing method according to the first embodiment of the present invention. FIGS. 5A to 5C are views (No. 4) illustrating the semiconductor wafer processing method according to the first embodiment of the present invention. FIGS. 6A to 6B are views (No. 1) illustrating a semiconductor wafer processing method according to the second embodiment of the present invention. FIGS. 7A to 7B are views (No. 2) showing the semiconductor wafer processing method according to the second embodiment of the present invention. FIGS. 8A to 8B are views (No. 1) illustrating a semiconductor wafer processing method according to the third embodiment of the present invention. FIGS. 9A to 9C are views (No. 2) showing the semiconductor wafer processing method according to the third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor wafer, 10a ... End part, 10b ... New end part, 10x ... Semiconductor chip, 11 ... Notch part, 12 ... Support body, 14 ... Ring-shaped cut part, A ... Element formation surface (front surface), B ... back, C ... effective chip area, E ... peripheral edge.

Claims (9)

A step of preparing a semiconductor wafer having a chip region in a central main portion of the surface;
Forming a ring-shaped cutout that penetrates the semiconductor wafer in a portion of a peripheral portion outside the chip region and along the outer periphery of the semiconductor wafer;
And a step of reducing the thickness of the semiconductor wafer by grinding the back surface of the semiconductor wafer. In the step of forming the cut portion and the step of reducing the thickness of the semiconductor wafer, the surface side of the semiconductor wafer is performed in a state of being attached to a support,
The semiconductor wafer processing method according to claim 1, wherein the cut portion is formed to penetrate from the back surface side to the front surface side of the semiconductor wafer. A step of preparing a semiconductor wafer having a chip region in a central main portion of the surface;
Forming a ring-shaped cutout having a depth that does not penetrate the semiconductor wafer from the back side of the semiconductor wafer, on the outer peripheral portion of the semiconductor wafer along the outer periphery of the chip region; and
Grinding the back surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer,
A method for processing a semiconductor wafer, characterized in that after the semiconductor wafer is ground, a groove in which the depth of the cut portion is reduced remains in the semiconductor wafer. 4. The method for processing a semiconductor wafer according to claim 3, wherein, in the step of forming the cut portion, the cut portion is formed deeper than a thickness for grinding the semiconductor wafer. A step of preparing a semiconductor wafer having a chip region in a central main portion of the surface;
Forming a ring-shaped cutout having a depth that does not penetrate the semiconductor wafer from the surface side of the semiconductor wafer, on the outer peripheral portion of the semiconductor wafer along the outer periphery of the chip region; and
A method of reducing the thickness of the semiconductor wafer by grinding the back surface of the semiconductor wafer until the cut portion is exposed. 6. The method of processing a semiconductor wafer according to claim 5, wherein, in the step of forming the cut portion, the cut portion is formed deeper than a thickness after grinding of the semiconductor wafer. 7. The semiconductor according to claim 1, wherein in the step of forming the cut portion, the cut portion is formed in a portion of the peripheral portion that is separated from the chip region with a predetermined dimension. Wafer processing method. 8. The method according to claim 1, further comprising a step of obtaining a plurality of individual semiconductor chips by dicing the semiconductor wafer after the step of reducing the thickness of the semiconductor wafer. A method for processing a semiconductor wafer as described in 1. The method for processing a semiconductor wafer according to claim 1, wherein in the step of reducing the thickness of the semiconductor wafer, the semiconductor wafer is thinned to a thickness of 100 μm or less.

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