JPS61249709A - Method of cutting semiconductor wafer - Google Patents

Method of cutting semiconductor wafer

Info

Publication number
JPS61249709A
JPS61249709A JP60093217A JP9321785A JPS61249709A JP S61249709 A JPS61249709 A JP S61249709A JP 60093217 A JP60093217 A JP 60093217A JP 9321785 A JP9321785 A JP 9321785A JP S61249709 A JPS61249709 A JP S61249709A
Authority
JP
Japan
Prior art keywords
cutting
semiconductor wafer
layer
adhesive
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60093217A
Other languages
Japanese (ja)
Inventor
佐川 敏男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP60093217A priority Critical patent/JPS61249709A/en
Publication of JPS61249709A publication Critical patent/JPS61249709A/en
Pending legal-status Critical Current

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  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Dicing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [発明の背景と目的] 本発明は、半導体素子を形成する際のチップを切断する
半導体ウェハのに切断方法の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Background and Objects of the Invention] The present invention relates to an improvement in a method for cutting a semiconductor wafer into chips for forming semiconductor elements.

一般に、半導体素子は、その素子特性を有効に利用する
ため素子自体に歪や傷が生じないように配慮しながら、
切断、加工等を行なっている。特に、化合物半導体等の
発光素子関係では材料的に脆く、転位、欠陥等も入り易
い等のため、素子加工にはj%lic’の注意が払われ
ている。
In general, semiconductor devices are manufactured by taking care not to cause distortion or scratches on the device itself in order to effectively utilize its device characteristics.
Cutting, processing, etc. Particularly, in the case of light emitting elements such as compound semiconductors, the material is brittle and easily susceptible to dislocations, defects, etc., and therefore a great deal of care is taken in processing the elements.

従来、例えば、Q、aP、G8AS、QaAsP等化合
物半導体からなる発光ダイオード等の素子をチップ化す
る場合、(1)(100)而を用い<110>方向に平
行、またはほぼ平行にダイシングする。(2) (10
0)面を用い<110>方向に対し45度またはほぼ4
5度に傾いた方向で切断する。あるいは、(3)ウェハ
を張り付けるテープまで切り込む等の方法がとられてい
た。以下これら従来の方法を第3図ないし第5図により
説明する。第3図は<110>方向にダイシングした(
100)面をチップする模式図て゛あり、(−1′)は
平面図、(ロ)は下方から圧力を加え切り込み食入れて
≠ツ・ブ化′する説明図、輌4図は<1(jQ>方向−
゛ダイシングしチップ化する模式図であり、(−1’)
は平面図、(0)は下方から1王力を加え切り込みを入
れてチップ化するπ(明図、第5図は接着テープまで切
込みを入れるところを示ず模式図であり、(イ)は平面
図、(ロ)は側面図である。
Conventionally, when chipping an element such as a light emitting diode made of a compound semiconductor such as Q, aP, G8AS, QaAsP, etc., (1) (100) is diced parallel to or almost parallel to the <110> direction. (2) (10
0) 45 degrees or approximately 4 degrees to the <110> direction using a plane
Cut at a 5 degree angle. Alternatively, (3) a method such as cutting down to the tape to which the wafer is attached has been taken. These conventional methods will be explained below with reference to FIGS. 3 to 5. Figure 3 shows dicing in the <110> direction (
There is a schematic diagram of chipping the 100) surface. jQ>direction-
゛This is a schematic diagram of dicing into chips, (-1')
(0) is a plan view, (0) is a π (clear diagram) where 1 royal force is applied from below and a cut is made to form a chip. A plan view, and (b) a side view.

図において、]は(100)基板、2は接着層である接
着テープ、3は圧力棒、4はクラック、5はチッピング
1.6は目詰り溝、7は接措糊、9は切断溝、10はへ
き開面である。そして、(1)の場合、第3図において
切断溝か深い程、また、切断速反が速い程チッピング5
か生じ易い。また、(2)の場合、第4図においてシー
ト(接着テープ2)の下面から加)’J= して素子を
チップ化する場合へき開面10か切込溝9の方向と約4
5痕傾いているため、へき開10に沿って割れる部分か
多く、希望する素子本来の立方体状の形状からすれてく
る。
In the figure, ] is (100) the substrate, 2 is the adhesive tape that is the adhesive layer, 3 is the pressure rod, 4 is the crack, 5 is the chipping 1.6 is the clogging groove, 7 is the adhesive, 9 is the cutting groove, 10 is a cleavage plane. In the case of (1), as shown in Fig. 3, the deeper the cutting groove and the faster the cutting speed, the more the chipping
It is easy to occur. In the case of (2), if the element is made into a chip by applying from the bottom surface of the sheet (adhesive tape 2) in FIG.
Since the marks 5 are tilted, there are many cracks along the cleavage 10, which causes the desired element to deviate from its original cubic shape.

さらに、クラック4は素子の本体まで入り込む進゛ 行
性の、クラック4になり易い。また、(3)の場合、第
5図においてダイシングブレードが接着テープの糊を巻
き込み切削力がなくなったところでウェハを切断するた
め、チッピング5を起こし切口は貝殻状の凸凹が発生す
る。この大きさは10μmから大きい時に50μmにも
達し素子の表面の形状、特性を著しく害している。
Furthermore, the crack 4 tends to become a progressive crack 4 that penetrates into the main body of the device. In the case of (3), in FIG. 5, the dicing blade winds up the adhesive tape and cuts the wafer when the cutting force is gone, causing chipping 5 and creating shell-like unevenness at the cut end. This size ranges from 10 .mu.m to 50 .mu.m in some cases, and seriously impairs the surface shape and characteristics of the element.

本発明は上記の状況に鑑みなされたものであり、切断、
面が平坦でチッピングが少なく、発光特性等の素子特性
に悪影響を及ぼすことが少なく品質が良好に切断できる
半導体ウェハの切断方法を提供することを目的としたも
のである。
The present invention was made in view of the above situation, and includes cutting,
The object of the present invention is to provide a method for cutting a semiconductor wafer with a flat surface, less chipping, less adverse effects on device characteristics such as light emitting characteristics, and high quality cutting.

[発明の概要] 本発明の半導体ウェハの切断方法は、接着層上に形成さ
れた半導体ウェハからグイシングツ−により切断溝を入
れて半導体チップを切断する場合に、上記接着層に至る
直前の深さまで上記切断溝が形成されることによりクラ
  ンクが入り切り離しが可能な切り残し層を残し上記
切断溝を入れ切断する方法である。即ち、ダイシングソ
ーにより半導体ウェハを切断する際に接着層(接着テー
プ)まで切断しない“で、接着層の直前のところまで切
断するようにし−Cチップのテープまたは接着層への切
り込みを防止し、接着剤によるプレートの目詰りを防止
1−ると共に、はぼ完全切断に近いため、へき開による
立方体形状からのずれをほとんど無くすことができる。
[Summary of the Invention] The method for cutting a semiconductor wafer of the present invention is such that when cutting a semiconductor chip by cutting a cutting groove from a semiconductor wafer formed on an adhesive layer using a cutting tool, the method cuts the semiconductor wafer to a depth just before reaching the adhesive layer. This is a method of cutting by inserting the above-mentioned cutting grooves, leaving an uncut layer that can be inserted by the crank and cut away. That is, when cutting a semiconductor wafer with a dicing saw, do not cut to the adhesive layer (adhesive tape), but cut to just before the adhesive layer - to prevent the C-chip from cutting into the tape or adhesive layer, In addition to preventing clogging of the plate due to adhesive, since the plate is almost completely cut, deviation from the cubic shape due to cleavage can be almost eliminated.

[実施例] 以下本発明の半導体ウェハの切断方法を実施例を用い従
来の方法を実施例と同部品は同符号で示し同部分の構造
の説明は省略し第1図により説明する。第1図は<11
0>方向に(100)而でGa A s結晶をダイシン
グした時の状況を示す模式図で、(()は平面図、(0
)は断面説明図、(/召は拡大図である。図において、
ブレードの回転数が1’0.000r’l)mで切断速
酊は、2M/Sで切り残し層8の切り残し寸法は接着テ
ープ2から10μm程度である。切断終了後、接着テー
プから取り外すとき(/9の破線のクラック4が切断時
にへき開に沿って生じ、それぞれのチップはばつを生じ
ることなく分離できた。即ち、チップの底部は切断時に
生じたへき開方向のクラックによりほぼ直角に切断され
、接着テープまたは接着剤等による目詰りがないため、
チッピング5が少なくへき開による形状のずれもほとん
ど生じない。上記実施例は接着層が接着テープの場合1
ζついて述べたが接着剤であっても同じである。
[Example] The semiconductor wafer cutting method of the present invention will be described below using an example, and the conventional method will be described with reference to FIG. Figure 1 is <11
This is a schematic diagram showing the situation when a GaAs crystal is diced in the (100) direction. (() is a plan view, ((0)
) is an explanatory cross-sectional view, (/ is an enlarged view. In the figure,
The number of revolutions of the blade is 1'0.000r'l)m, the cutting speed is 2 M/S, and the uncut dimension of the uncut layer 8 is about 10 μm from the adhesive tape 2. After cutting, when removing the adhesive tape from the adhesive tape (/9), a crack 4 (indicated by the broken line of /9) was generated along the cleavage at the time of cutting, and each chip could be separated without any damage. In other words, the bottom of the chip It is cut at almost right angles due to directional cracks, and there is no clogging caused by adhesive tape or adhesive, etc.
There is little chipping 5 and almost no deviation in shape due to cleavage occurs. The above example is 1 when the adhesive layer is an adhesive tape.
Although I mentioned ζ, the same applies to adhesives.

このように本実施例の半導体ウェハの切断方法は、半導
体チップに切断溝を入れて切断の場合に、接着層に至る
直前の深さでクラックが入ることにより切り離しが可能
な切り残し層を残し切断溝を入れるようにしたので、切
断面が平坦でチッピングが少な〈従来困難であったチッ
プ周辺のパターンの使用が可能となり無駄のないパター
ン面積を確保できばりの発生もなく、素子特性に悪影響
を及ぼすことが少ない良好な品質を1qることができる
In this way, the semiconductor wafer cutting method of this embodiment is such that when a semiconductor chip is cut by cutting grooves, a crack occurs at a depth just before reaching the adhesive layer, leaving an uncut layer that can be separated. Since cutting grooves are provided, the cut surface is flat and there is little chipping. It is now possible to use patterns around the chip, which was difficult in the past, ensuring a lean pattern area and eliminating the occurrence of burrs, which adversely affect device characteristics. 1q can have good quality with less impact.

上記実施例は、GaAsの場合について述べたが、Si
、Geなどの半導体結晶及び他の化合物半導体、イオン
結合性物質等へき開性の強い物質の切1析に応用できる
In the above embodiment, the case of GaAs was described, but Si
It can be applied to the cutting and analysis of materials with strong cleavage properties, such as semiconductor crystals such as , Ge, other compound semiconductors, and ionic bonding substances.

第2図は仙の実施例で、<110>方向から45度傾い
た<100>方向に切断した状況の模式図で(−1’)
は平面図、([])は切断説明図、(/→は拡大図−(
”ある。切り込み法線に対し45度傾いた、<110>
方向のへぎ開に沿ってクラック4か入りこの寸法は5μ
mで切断応力の関係でばつの残らない方向に伝播してお
り、接着テープ2からチップを取り外すことにより、チ
ッ゛プは完全に分離することができた。また、切り残し
層8を10μ■とじた場合へき開による立方体のずれは
5μm以下に押えることができた。これらは半導体月利
の物性により責なり面方位、へき開の方向、へき開性硬
さ、脆さ等により異り、その材料により適切な切断速度
、切り残し代を定める必要がある。本実施例も上記実施
例と同様の作用効果を有する。
Figure 2 is an example of Sen, and is a schematic diagram of the situation where it is cut in the <100> direction tilted 45 degrees from the <110> direction (-1').
is a plan view, ([]) is a cutting diagram, (/→ is an enlarged view - (
"Yes. Tilt 45 degrees to the incision normal, <110>
There are 4 cracks along the direction of the separation.This dimension is 5μ
At m, the chips propagated in a direction where no blemish was left due to the cutting stress, and by removing the chip from the adhesive tape 2, the chip could be completely separated. Further, when the uncut layer 8 was closed by 10 μm, the displacement of the cube due to cleavage could be suppressed to 5 μm or less. These vary depending on the physical properties of the semiconductor, such as surface orientation, cleavage direction, cleavage hardness, brittleness, etc., and it is necessary to determine an appropriate cutting speed and uncut allowance depending on the material. This example also has the same effects as the above example.

[発明の効果] 以上記述した如く本発明の半導体ウェハの切断方法によ
れば、切断面が平坦でチッピングか少なくばりか発生す
ることなく特性の良好な晶質に切断できる効果を有する
ものである。
[Effects of the Invention] As described above, the method for cutting a semiconductor wafer of the present invention has the effect that the cut surface is flat and the wafer can be cut into a crystalline material with good properties without chipping or burrs. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図はそれぞれ本発明の半導体ウェハの切断
方法によるチッピング化するところの模式図であり第1
図は<110>方向に、第2図は<100>方向にダイ
シング時を示し、それぞれイ)は平面図、(ロ)は断面
説明図、(/〜は拡大図、第3図ないし第5図は従来の
方法によるチップ化するところを承ず模式図であり第3
図は<110>方向に、第4図は<:106>方向にダ
イシング時を示し、それぞれ(()は平面図、(D)は
切り込みを入れる説明図、第5図は接着テープまで切断
溝を入れる場合を示してイ)は平面図、(ロ)は断面説
明図である。 2・・・接着テープ、4・・・クラック、8・・・切り
残し層、9・・・切断溝。 代理人  弁理士  佐 藤 不二雄 第 2 聞 (イ) u (O)− (l\) 第 3 図 (イ)
FIG. 1 and FIG. 2 are schematic diagrams of chipping by the semiconductor wafer cutting method of the present invention, respectively.
The figure shows dicing in the <110> direction, and Fig. 2 shows dicing in the <100> direction, respectively. The figure is a schematic diagram of the process of making chips using the conventional method.
The figure shows dicing in the <110> direction, and Figure 4 shows dicing in the <:106> direction. A) is a plan view, and (b) is a cross-sectional explanatory view. 2...Adhesive tape, 4...Crack, 8...Uncut layer, 9...Cut groove. Agent Patent Attorney Fujio Sato 2nd hearing (a) u (O)- (l\) Figure 3 (a)

Claims (4)

【特許請求の範囲】[Claims] (1)接着層上に形成された半導体ウェハからダイシン
グソーにより切断溝を入れて半導体チップを切断する方
法において、上記接着層に至る直前の深さまで上記切断
溝が形成されることによりクラックが入り切り離しが可
能な切り残し層を残し上記切断層を入れ切断することを
特徴とする半導体ウェハの切断方法。
(1) In a method of cutting semiconductor chips by cutting grooves using a dicing saw from a semiconductor wafer formed on an adhesive layer, cracks may occur due to the cutting grooves being formed to a depth just before reaching the adhesive layer. A method for cutting a semiconductor wafer, comprising inserting and cutting the cutting layer while leaving an uncut layer that can be separated.
(2)上記半導体ウェハの上記切り残し層が100μm
以下である特許請求の範囲第1項記載の半導体ウェハの
切断方法。
(2) The uncut layer of the semiconductor wafer is 100 μm
A method for cutting a semiconductor wafer according to claim 1, which is as follows.
(3)上記接着層が粘着テープもしくは接着剤である特
許請求の範囲第1項記載の半導体ウェハの切断方法。
(3) The method for cutting a semiconductor wafer according to claim 1, wherein the adhesive layer is an adhesive tape or an adhesive.
(4)上記半導体ウェハがシリコンもしくは化合物半導
体である特許請求の範囲第1項記載の半導体ウェハの切
断方法。
(4) The method for cutting a semiconductor wafer according to claim 1, wherein the semiconductor wafer is silicon or a compound semiconductor.
JP60093217A 1985-04-30 1985-04-30 Method of cutting semiconductor wafer Pending JPS61249709A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60093217A JPS61249709A (en) 1985-04-30 1985-04-30 Method of cutting semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60093217A JPS61249709A (en) 1985-04-30 1985-04-30 Method of cutting semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS61249709A true JPS61249709A (en) 1986-11-06

Family

ID=14076390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60093217A Pending JPS61249709A (en) 1985-04-30 1985-04-30 Method of cutting semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS61249709A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6282008A (en) * 1985-10-04 1987-04-15 三菱電機株式会社 Breaking device for semiconductor wafer
JP2001319897A (en) * 2000-05-11 2001-11-16 Disco Abrasive Syst Ltd Dividing method of semiconductor wafer
JP2011181770A (en) * 2010-03-02 2011-09-15 Fuji Electric Co Ltd Semiconductor device and method of manufacturing semiconductor device
JP2020113564A (en) * 2019-01-08 2020-07-27 株式会社ディスコ Manufacturing method of chip

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6282008A (en) * 1985-10-04 1987-04-15 三菱電機株式会社 Breaking device for semiconductor wafer
JPH0262367B2 (en) * 1985-10-04 1990-12-25 Mitsubishi Electric Corp
JP2001319897A (en) * 2000-05-11 2001-11-16 Disco Abrasive Syst Ltd Dividing method of semiconductor wafer
JP2011181770A (en) * 2010-03-02 2011-09-15 Fuji Electric Co Ltd Semiconductor device and method of manufacturing semiconductor device
CN102194863A (en) * 2010-03-02 2011-09-21 富士电机控股株式会社 Semiconductor device and method of manufacturing semiconductor device
US9355858B2 (en) 2010-03-02 2016-05-31 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device
JP2020113564A (en) * 2019-01-08 2020-07-27 株式会社ディスコ Manufacturing method of chip

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